 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| hitachi microcomputer h8/3032 series hardware manual omc942723169
preface the h8/3032 series is a series of high-performance single-chip microcontrollers that integrate system supporting functions together with an h8/300h cpu core. the h8/300h cpu has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space.* the on-chip system supporting functions include rom, ram, a 16-bit integrated timer unit (itu), a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, i/o ports, and other facilities. the three operating modes offer a choice of expanded mode and single-chip mode, enabling the h8/3032 series to adapt quickly and flexibly to a variety of conditions. this manual describes the h8/3032 series hardware. for details of the instruction set, refer to the h8/300h programming manual. note: * the h8/3032 series has a maximum address space of 1 mbyte. contents section 1 overview ..................................................................................................... 1 1.1 overview ........................................................................................................................ 1 1.2 block diagram................................................................................................................ 5 1.3 pin description ............................................................................................................... 6 1.3.1 pin arrangement............................................................................................. 6 1.3.2 pin functions .................................................................................................. 7 1.4 pin functions .................................................................................................................. 10 section 2 cpu ............................................................................................................... 15 2.1 overview ........................................................................................................................ 15 2.1.1 features........................................................................................................... 15 2.1.2 differences from h8/300 cpu ....................................................................... 16 2.2 cpu operating modes.................................................................................................... 17 2.3 address space................................................................................................................. 18 2.4 register configuration.................................................................................................... 19 2.4.1 overview......................................................................................................... 19 2.4.2 general registers............................................................................................ 20 2.4.3 control registers ............................................................................................ 21 2.4.4 initial cpu register values ............................................................................ 22 2.5 data formats................................................................................................................... 23 2.5.1 general register data formats....................................................................... 23 2.5.2 memory data formats.................................................................................... 24 2.6 instruction set................................................................................................................. 26 2.6.1 instruction set overview ................................................................................ 26 2.6.2 instructions and addressing modes................................................................ 27 2.6.3 tables of instructions classified by function ................................................ 28 2.6.4 basic instruction formats ............................................................................... 38 2.6.5 notes on use of bit manipulation instructions .............................................. 39 2.7 addressing modes and effective address calculation .................................................. 39 2.7.1 addressing modes .......................................................................................... 39 2.7.2 effective address calculation ........................................................................ 42 2.8 processing states ............................................................................................................ 46 2.8.1 overview......................................................................................................... 46 2.8.2 program execution state ................................................................................ 47 2.8.3 exception-handling state............................................................................... 47 2.8.4 exception-handling sequences ...................................................................... 49 2.8.5 reset state ...................................................................................................... 50 2.8.6 power-down state .......................................................................................... 50 2.9 basic operational timing ............................................................................................... 51 2.9.1 overview......................................................................................................... 51 2.9.2 on-chip memory access timing................................................................... 51 2.9.3 on-chip supporting module access timing ................................................. 53 2.9.4 access to external address space.................................................................. 54 section 3 mcu operating modes ........................................................................... 55 3.1 overview ........................................................................................................................ 55 3.1.1 operating mode selection .............................................................................. 55 3.1.2 register configuration.................................................................................... 56 3.2 mode control register (mdcr) .................................................................................... 57 3.3 system control register (syscr)................................................................................. 58 3.4 operating mode descriptions......................................................................................... 60 3.4.1 mode 1 ............................................................................................................ 60 3.4.2 mode 2 ............................................................................................................ 60 3.4.3 mode 3 ............................................................................................................ 60 3.5 pin functions in each operating mode.......................................................................... 61 3.6 memory map in each operating mode.......................................................................... 61 section 4 exception handling .................................................................................. 65 4.1 overview ........................................................................................................................ 65 4.1.1 exception handling types and priority.......................................................... 65 4.1.2 exception handling operation ....................................................................... 65 4.1.3 exception vector table................................................................................... 66 4.2 reset ........................................................................................................................ 67 4.2.1 overview......................................................................................................... 67 4.2.2 reset sequence ............................................................................................... 67 4.2.3 interrupts after reset....................................................................................... 69 4.3 interrupts ........................................................................................................................ 70 4.4 trap instruction............................................................................................................... 71 4.5 stack status after exception handling ........................................................................... 72 4.6 notes on stack usage ..................................................................................................... 73 section 5 interrupt controller ................................................................................... 75 5.1 overview ........................................................................................................................ 75 5.1.1 features........................................................................................................... 75 5.1.2 block diagram................................................................................................ 76 5.1.3 pin configuration............................................................................................ 77 5.1.4 register configuration.................................................................................... 77 5.2 register descriptions...................................................................................................... 78 5.2.1 system control register (syscr)................................................................. 78 5.2.2 interrupt priority registers a and b (ipra, iprb) ....................................... 79 5.2.3 irq status register (isr) .............................................................................. 85 5.2.4 irq enable register (ier)............................................................................. 86 5.2.5 irq sense control register (iscr) ............................................................... 87 5.3 interrupt sources............................................................................................................. 88 5.3.1 external interrupts .......................................................................................... 88 5.3.2 internal interrupts ........................................................................................... 89 5.3.3 interrupt vector table ..................................................................................... 89 5.4 interrupt operation ......................................................................................................... 92 5.4.1 interrupt handling process ............................................................................. 92 5.4.2 interrupt sequence .......................................................................................... 97 5.4.3 interrupt response time................................................................................. 98 5.5 usage notes .................................................................................................................... 99 5.5.1 contention between interrupt and interrupt-disabling instruction ................ 99 5.5.2 instructions that inhibit interrupts .................................................................. 100 5.5.3 interrupts during eepmov instruction execution ........................................ 100 section 6 bus controller ............................................................................................ 101 6.1 overview ........................................................................................................................ 101 6.1.1 features........................................................................................................... 101 6.1.2 block diagram................................................................................................ 102 6.1.3 input/output pins............................................................................................ 103 6.1.4 register configuration.................................................................................... 103 6.2 register descriptions...................................................................................................... 104 6.2.1 access state control register (astcr)........................................................ 104 6.2.2 wait control register (wcr)......................................................................... 105 6.2.3 wait state controller enable register (wcer)............................................. 106 6.3 operation ........................................................................................................................ 107 6.3.1 area division.................................................................................................. 107 6.3.2 bus control signal timing ............................................................................. 109 6.3.3 wait modes ..................................................................................................... 111 6.3.4 interconnections with memory (example)..................................................... 117 6.4 usage notes .................................................................................................................... 118 6.4.1 register write timing .................................................................................... 118 section 7 i/o ports ....................................................................................................... 119 7.1 overview ........................................................................................................................ 119 7.2 port 1 ........................................................................................................................ 122 7.2.1 overview......................................................................................................... 122 7.2.2 register descriptions...................................................................................... 123 7.2.3 pin functions in each mode........................................................................... 124 7.3 port 2 ........................................................................................................................ 126 7.3.1 overview......................................................................................................... 126 7.3.2 register descriptions...................................................................................... 127 7.3.3 pin functions in each mode........................................................................... 128 7.3.4 input pull-up transistors................................................................................ 130 7.4 port 3 ........................................................................................................................ 131 7.4.1 overview......................................................................................................... 131 7.4.2 register descriptions...................................................................................... 131 7.4.3 pin functions in each mode........................................................................... 133 7.5 port 5 ........................................................................................................................ 134 7.5.1 overview......................................................................................................... 134 7.5.2 register descriptions...................................................................................... 134 7.5.3 pin functions in each mode........................................................................... 137 7.5.4 input pull-up transistors................................................................................ 138 7.6 port 6 ........................................................................................................................ 139 7.6.1 overview......................................................................................................... 139 7.6.2 register descriptions...................................................................................... 139 7.6.3 pin functions in each mode........................................................................... 141 7.7 port 7 ........................................................................................................................ 144 7.7.1 overview......................................................................................................... 144 7.7.2 register description ....................................................................................... 145 7.8 port 8 ........................................................................................................................ 146 7.8.1 overview......................................................................................................... 146 7.8.2 register descriptions...................................................................................... 147 7.8.3 pin functions .................................................................................................. 148 7.9 port 9 ........................................................................................................................ 150 7.9.1 overview......................................................................................................... 150 7.9.2 register descriptions...................................................................................... 150 7.9.3 pin functions .................................................................................................. 152 7.10 port a ........................................................................................................................ 153 7.10.1 overview......................................................................................................... 153 7.10.2 register descriptions...................................................................................... 154 7.10.3 pin functions ................................................................................................. 156 7.11 port b ........................................................................................................................ 161 7.11.1 overview......................................................................................................... 161 7.11.2 register descriptions...................................................................................... 161 7.11.3 pin functions .................................................................................................. 163 section 8 16-bit integrated timer unit (itu) ..................................................... 169 8.1 overview ........................................................................................................................ 169 8.1.1 features........................................................................................................... 169 8.1.2 block diagrams .............................................................................................. 172 8.1.3 input/output pins............................................................................................ 177 8.1.4 register configuration.................................................................................... 178 8.2 register descriptions...................................................................................................... 181 8.2.1 timer start register (tstr) .......................................................................... 181 8.2.2 timer synchro register (tsnc) .................................................................... 182 8.2.3 timer mode register (tmdr)....................................................................... 184 8.2.4 timer function control register (tfcr) ...................................................... 187 8.2.5 timer output master enable register (toer) .............................................. 189 8.2.6 timer output control register (tocr)......................................................... 192 8.2.7 timer counters (tcnt) ................................................................................. 193 8.2.8 general registers (gra, grb) ..................................................................... 194 8.2.9 buffer registers (bra, brb) ........................................................................ 195 8.2.10 timer control registers (tcr) ...................................................................... 196 8.2.11 timer i/o control register (tior)................................................................ 198 8.2.12 timer status register (tsr)........................................................................... 200 8.2.13 timer interrupt enable register (tier)......................................................... 203 8.3 cpu interface ................................................................................................................. 205 8.3.1 16-bit accessible registers............................................................................ 205 8.3.2 8-bit accessible registers.............................................................................. 207 8.4 operation ........................................................................................................................ 209 8.4.1 overview......................................................................................................... 209 8.4.2 basic functions............................................................................................... 210 8.4.3 synchronization .............................................................................................. 220 8.4.4 pwm mode .................................................................................................... 222 8.4.5 reset-synchronized pwm mode ................................................................... 226 8.4.6 complementary pwm mode.......................................................................... 229 8.4.7 phase counting mode..................................................................................... 239 8.4.8 buffering......................................................................................................... 241 8.4.9 itu output timing......................................................................................... 248 8.5 interrupts ........................................................................................................................ 250 8.5.1 setting of status flags .................................................................................... 250 8.5.2 clearing of status flags.................................................................................. 252 8.5.3 interrupt sources............................................................................................. 253 8.6 usage notes .................................................................................................................... 254 section 9 programmable timing pattern controller ......................................... 269 9.1 overview ........................................................................................................................ 269 9.1.1 features........................................................................................................... 269 9.1.2 block diagram................................................................................................ 270 9.1.3 tpc pins ......................................................................................................... 271 9.1.4 registers ......................................................................................................... 272 9.2 register descriptions...................................................................................................... 273 9.2.1 port a data direction register (paddr) ...................................................... 273 9.2.2 port a data register (padr) ......................................................................... 273 9.2.3 port b data direction register (pbddr) ...................................................... 274 9.2.4 port b data register (pbdr) ......................................................................... 274 9.2.5 next data register a (ndra)....................................................................... 275 9.2.6 next data register b (ndrb) ....................................................................... 277 9.2.7 next data enable register a (ndera) ........................................................ 279 9.2.8 next data enable register b (nderb)......................................................... 280 9.2.9 tpc output control register (tpcr)............................................................ 281 9.2.10 tpc output mode register (tpmr).............................................................. 284 9.3 operation ........................................................................................................................ 286 9.3.1 overview......................................................................................................... 286 9.3.2 output timing................................................................................................. 287 9.3.3 normal tpc output........................................................................................ 288 9.3.4 non-overlapping tpc output........................................................................ 290 9.3.5 tpc output triggering by input capture....................................................... 292 9.4 usage notes .................................................................................................................... 293 9.4.1 operation of tpc output pins........................................................................ 293 9.4.2 note on non-overlapping output .................................................................. 293 section 10 watchdog timer ........................................................................................ 295 10.1 overview ........................................................................................................................ 295 10.1.1 features........................................................................................................... 295 10.1.2 block diagram................................................................................................ 296 10.1.3 pin configuration............................................................................................ 296 10.1.4 register configuration.................................................................................... 297 10.2 register descriptions...................................................................................................... 298 10.2.1 timer counter (tcnt)................................................................................... 298 10.2.2 timer control/status register (tcsr)........................................................... 299 10.2.3 reset control/status register (rstcsr) ...................................................... 301 10.2.4 notes on register access ............................................................................... 303 10.3 operation ........................................................................................................................ 305 10.3.1 watchdog timer operation............................................................................. 305 10.3.2 interval timer operation ................................................................................ 306 10.3.3 timing of setting of overflow flag (ovf).................................................... 307 10.3.4 timing of setting of watchdog timer reset bit (wrst) ............................. 308 10.4 interrupts ........................................................................................................................ 309 10.5 usage notes .................................................................................................................... 309 section 11 serial communication interface ........................................................... 311 11.1 overview ........................................................................................................................ 311 11.1.1 features........................................................................................................... 311 11.1.2 block diagram................................................................................................ 313 11.1.3 input/output pins............................................................................................ 314 11.1.4 register configuration.................................................................................... 314 11.2 register descriptions...................................................................................................... 315 11.2.1 receive shift register (rsr) ......................................................................... 315 11.2.2 receive data register (rdr)......................................................................... 315 11.2.3 transmit shift register (tsr)........................................................................ 316 11.2.4 transmit data register (tdr) ....................................................................... 316 11.2.5 serial mode register (smr) .......................................................................... 317 11.2.6 serial control register (scr) ........................................................................ 321 11.2.7 serial status register (ssr) ........................................................................... 325 11.2.8 bit rate register (brr) ................................................................................. 329 11.3 operation ........................................................................................................................ 338 11.3.1 overview......................................................................................................... 338 11.3.2 operation in asynchronous mode.................................................................. 340 11.3.3 multiprocessor communication ..................................................................... 349 11.3.4 synchronous operation .................................................................................. 356 11.4 sci interrupts.................................................................................................................. 365 11.5 usage notes .................................................................................................................... 366 section 12 a/d converter ............................................................................................ 371 12.1 overview ........................................................................................................................ 371 12.1.1 features........................................................................................................... 371 12.1.2 block diagram................................................................................................ 372 12.1.3 input pins ........................................................................................................ 373 12.1.4 register configuration.................................................................................... 374 12.2 register descriptions...................................................................................................... 375 12.2.1 a/d data registers a to d (addra to addrd)........................................ 375 12.2.2 a/d control/status register (adcsr) .......................................................... 376 12.2.3 a/d control register (adcr) ....................................................................... 379 12.3 cpu interface ................................................................................................................. 380 12.4 operation ........................................................................................................................ 381 12.4.1 single mode (scan = 0) ............................................................................... 381 12.4.2 scan mode (scan = 1).................................................................................. 383 12.4.3 input sampling and a/d conversion time .................................................... 385 12.4.4 external trigger input timing........................................................................ 386 12.5 interrupts ........................................................................................................................ 387 12.6 usage notes .................................................................................................................... 387 section 13 ram ............................................................................................................. 389 13.1 overview ........................................................................................................................ 389 13.1.1 block diagram................................................................................................ 389 13.1.2 register configuration.................................................................................... 390 13.2 system control register (syscr)................................................................................. 391 13.3 operation ........................................................................................................................ 392 13.3.1 mode 1 ............................................................................................................ 392 13.3.2 modes 2 and 3................................................................................................. 392 section 14 rom ............................................................................................................. 393 14.1 overview ........................................................................................................................ 393 14.1.1 block diagram................................................................................................ 393 14.2 prom mode................................................................................................................... 394 14.2.1 prom mode setting ...................................................................................... 394 14.2.2 socket adapter and memory map.................................................................. 394 14.3 programming .................................................................................................................. 397 14.3.1 programming and verification........................................................................ 397 14.3.2 programming precautions............................................................................... 402 14.4 reliability of programmed data..................................................................................... 403 section 15 clock pulse generator ............................................................................. 405 15.1 overview ........................................................................................................................ 405 15.1.1 block diagram................................................................................................ 405 15.2 oscillator circuit ............................................................................................................ 406 15.2.1 connecting a crystal resonator ..................................................................... 406 15.2.2 external clock input....................................................................................... 408 15.3 duty adjustment circuit................................................................................................. 410 15.4 prescalers ........................................................................................................................ 410 section 16 power-down state .................................................................................... 411 16.1 overview ........................................................................................................................ 411 16.2 register configuration.................................................................................................... 412 16.2.1 system control register (syscr)................................................................. 412 16.3 sleep mode ..................................................................................................................... 414 16.3.1 transition to sleep mode................................................................................ 414 16.3.2 exit from sleep mode..................................................................................... 414 16.4 software standby mode ................................................................................................. 415 16.4.1 transition to software standby mode ............................................................ 415 16.4.2 exit from software standby mode ................................................................. 415 16.4.3 selection of waiting time for exit from software standby mode ................ 416 16.4.4 sample application of software standby mode ............................................ 417 16.4.5 note................................................................................................................. 417 16.5 hardware standby mode ................................................................................................ 418 16.5.1 transition to hardware standby mode........................................................... 418 16.5.2 exit from hardware standby mode................................................................ 418 16.5.3 timing for hardware standby mode.............................................................. 418 section 17 electrical characteristics ........................................................................ 419 17.1 absolute maximum ratings ........................................................................................... 419 17.2 electrical characteristics ................................................................................................ 420 17.2.1 dc characteristics .......................................................................................... 420 17.2.2 ac characteristics .......................................................................................... 430 17.2.3 a/d conversion characteristics ..................................................................... 437 17.3 operational timing......................................................................................................... 438 17.3.1 bus timing ..................................................................................................... 438 17.3.2 control signal timing .................................................................................... 442 17.3.3 clock timing .................................................................................................. 444 17.3.4 tpc and i/o port timing................................................................................ 444 17.3.5 itu timing ..................................................................................................... 445 17.3.6 sci input/output timing................................................................................ 446 appendix a instruction set ............................................................................................ 447 a.1 instruction list................................................................................................................ 447 a.2 operating code maps ..................................................................................................... 462 a.3 number of states required for execution...................................................................... 465 appendix b register field ............................................................................................. 474 b.1 register addresses and bit names................................................................................. 474 b.2 register descriptions...................................................................................................... 482 appendix c i/o port block diagrams ........................................................................ 532 c.1 port 1 block diagram ..................................................................................................... 532 c.2 port 2 block diagram ..................................................................................................... 533 c.3 port 3 block diagram ..................................................................................................... 534 c.4 port 5 block diagram ..................................................................................................... 535 c.5 port 6 block diagram ..................................................................................................... 536 c.6 port 7 block diagram ..................................................................................................... 538 c.7 port 8 block diagram ..................................................................................................... 539 c.8 port 9 block diagram ..................................................................................................... 540 c.9 port a block diagram .................................................................................................... 543 c.10 port b block diagram .................................................................................................... 546 appendix d pin states ..................................................................................................... 550 d.1 port states in each mode................................................................................................ 550 d.2 pin states at reset........................................................................................................... 552 appendix e timing of transition to and recovery from hardware standby mode .............................................................. 555 appendix f package dimensions ................................................................................ 556 section 1 overview 1.1 overview the h8/3032 series is a series of microcontrollers (mcus) that integrate system supporting functions together with an h8/300h cpu core having an original hitachi architecture. the h8/300h cpu has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space. *1 its instruction set is upward-compatible at the object-code level with the h8/300 cpu, enabling easy porting of software from the h8/300 series. the on-chip system supporting functions include rom, ram, a 16-bit integrated timer unit (itu), a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, i/o ports, and other facilities. the three members of the h8/3032 series are the h8/3032, the h8/3031, and the h8/3030. the h8/3032 has 64 kbytes of rom and 2 kbytes of ram. the h8/3031 has 32 kbytes of rom and 1 kbyte of ram. the h8/3030 has 16 kbytes of rom and 512 bytes of ram. three mcu operating modes offer a choice of data bus width and address space size. the modes (modes 1 to 3) include a single-chip mode and expanded mode. in addition to the masked-rom versions of the h8/3032 series, the h8/3032 has a ztat *2 version with user-programmable on-chip prom. this version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. table 1-1 summarizes the features of the h8/3032 series. notes: 1. the h8/3032 series has a maximum address space of 1 mbyte. 2. ztat (zero turn-around time) is a trademark of hitachi, ltd. 1 table 1-1 features feature description cpu upward-compatible with the h8/300 cpu at the object-code level general-register machine sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) high-speed operation maximum clock rate: 16 mhz add/subtract: 125 ns multiply/divide: 875 ns two cpu operating modes normal mode (64-kbyte address space) advanced mode (1-mbyte address space) instruction features 8/16/32-bit data transfer, arithmetic, and logic instructions signed and unsigned multiply instructions (8 bits 8 bits, 16 bits 16 bits) signed and unsigned divide instructions (16 bits ? 8 bits, 32 bits ? 16 bits) bit accumulator function bit manipulation instructions with register-indirect specification of bit positions memory h8/3032 rom: 64 kbytes ram: 2 kbytes h8/3031 rom: 32 kbytes ram: 1 kbyte h8/3030 rom: 16 kbytes ram: 512 bytes interrupt six external interrupt pins: nmi, irq 0 to irq 4 controller 21 internal interrupts three selectable interrupt priority levels bus controller address space can be partitioned into eight areas, with independent bus specifications in each area two-state or three-state access selectable for each area selection of four wait modes 2 table 1-1 features (cont) feature description 16-bit integrated five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 timer unit (itu) pulse inputs 16-bit timer counter (channels 0 to 4) two multiplexed output compare/input capture pins (channels 0 to 4) operation can be synchronized (channels 0 to 4) pwm mode available (channels 0 to 4) phase counting mode available (channel 2) buffering available (channels 3 and 4) reset-synchronized pwm mode available (channels 3 and 4) complementary pwm mode available (channels 3 and 4) programmable maximum 16-bit pulse output, using itu as time base timing pattern up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) controller (tpc) non-overlap mode available watchdog reset signal can be generated by overflow timer (wdt), reset signal can be output externally 1 channel usable as an interval timer serial selection of asynchronous or synchronous mode communication full duplex: can transmit and receive simultaneously interface (sci), on-chip baud-rate generator 2 channels a/d converter resolution: 10 bits eight channels, with selection of single or scan mode variable analog conversion voltage range sample-and-hold function can be externally triggered i/o ports 55 input/output pins 8 input-only pins 3 table 1-1 features (cont) feature description operating modes three mcu operating modes address address bus mode space pins width mode 1 1 mbyte a 0 to a 19 8 bits mode 2 64 kbytes mode 3 1 mbyte power-down sleep mode state software standby mode hardware standby mode other features on-chip clock oscillator product lineup model package rom HD6473032F 80-pin qfp (fp-80a) prom hd6473032tf 80-pin tqfp (tfp-80c) hd6433032f 80-pin qfp (fp-80a) mask rom hd6433032tf 80-pin tqfp (tfp-80c) hd6433031f 80-pin qfp (fp-80a) mask rom hd6433031tf 80-pin tqfp (tfp-80c) hd6433030f 80-pin qfp (fp-80a) mask rom hd6433030tf 80-pin tqfp (tfp-80c) 4 1.2 block diagram figure 1-1 shows an internal block diagram. figure 1-1 block diagram p7 7 /an 7 p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 v ref av cc av ss pa 7 /tiocb 2 pa 6 /tioca 2 pa 5 /tiocb 1 pa 4 /tioca 1 pa 3 /tiocb 0 /tkckd pa 2 /tioca 0 /tclkc pa 1 /tclkb pa 0 /tclka pb 7 /tp 15 / adtrg pb 6 /tp 14 pb 5 /tp 13 /tocxb 4 pb 4 /tp 12 /tocxa 4 pb 2 /tp 11 /tiocb 4 pb 2 /tp 10 /tioca 4 pb 1 /tp 9 /tiocb 3 pb 0 /tp 8 /tioca 3 p2 7 /a 15 p2 6 /a 14 p2 5 /a 13 p2 4 /a 12 p2 3 /a 11 p2 2 /a 10 p2 1 /a 9 p2 0 /a 8 p1 7 /a 7 p1 6 /a 6 p1 5 /a 5 p1 4 /a 4 p1 3 /a 3 p1 2 /a 2 p1 1 /a 1 p1 0 /a 0 p9 4 /sck/irq 4 p9 2 /rxd p9 0 /txd p5 3 /a 15 p5 2 /a 16 p5 1 /a 17 p5 0 /a 18 data bus (lower) bus controller clock osc. h8/300h cpu prom * (or masked rom) ram 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) interrupt controller watchdog timer (wdt) serial communication interface (sci) 1 channel a/d converter port 3 p6 5 / wr p6 4 / rd p6 3 / as p6 0 / wait p8 3 /irq 3 p8 2 /irq 2 p8 1 /irq 1 p8 0 /irq 0 md 1 md 0 extal xtal ? stby res reso nmi v cc v cc v ss v ss v ss p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 port 2 port 1 port 5 port 9 port 7 port a port b port 8 port 6 address bus data bus (upper) note: prom version is available only in the h8/3032 series. 5 1.3 pin description 1.3.1 pin arrangement figure 1-2 shows the pin arrangement of the h8/3032 series, fp-80a and tfp-80c package. figure 1-2 pin arrangement (fp-80a, tfp-80c, top view) p7 1 /an 1 p7 0 /an 0 av ss reso p6 5 / wr p6 4 / rd p6 3 / as v cc xtal extal v ss nmi res stby ? md 1 md 0 p6 0 / wait p5 3 /a 19 p5 2 /a 18 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pb 0 /tp 8 /tioca 3 pb 1 /tp 9 /tiocb 3 pb 2 /tp 10 /tioca 4 pb 3 /tp 11 /tiocb 4 pb 4 /tp 12 /tocxa 4 pb 5 /tp 13 /tocxb 4 pb 6 /tp 14 pb 7 /tp 15 / adtrg p9 0 /txd p9 2 /rxd p9 4 /sck/irq 4 v ss p3 0 /d 0 p3 1 /d 1 p3 2 /d 2 p3 3 /d 3 p3 4 /d 4 p3 5 /d 5 p3 6 /d 6 p3 7 /d 7 pa 7 /tp 7 /tiocb 2 pa 6 /tp 6 /tioca 2 pa 5 /tp 5 /tiocb 1 pa 4 /tp 4 /tioca 1 pa 3 /tp 3 /iocb 0 /tclkd pa 2 /tp 2 /tioca 0 /tclkc pa 1 /tp 1 /tclkb pa 0 /tp 0 /tclka p8 3 /irq 3 p8 2 /irq 2 p8 1 /irq 1 p8 0 /irq 0 av cc v ref p7 7 /an 7 p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 v cc p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 p5 0 /a 16 p5 1 /a 17 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 top view (fp-80a, tfp-80c) 6 1.3.2 pin functions pin assignments in each mode: table 1-2 lists the fp-80a and tfp-80c pin assignments in each mode. table 1-2 fp-80a and tfp-80c pin assignments in each mode pin pin name no. mode 1 mode 2 mode 3 prom mode 1pb 0 /tp 8 /tioca 3 pb 0 /tp 8 /tioca 3 pb 0 /tp 8 /tioca 3 nc 2pb 1 /tp 9 /tiocb 3 pb 1 /tp 9 /tiocb 3 pb 1 /tp 9 /tiocb 3 nc 3pb 2 /tp 10 /tioca 4 pb 2 /tp 10 /tioca 4 pb 2 /tp 10 /tioca 4 nc 4pb 3 /tp 11 /tiocb 4 pb 3 /tp 11 /tiocb 4 pb 3 /tp 11 /tiocb 4 nc 5pb 4 /tp 12 /tocxa 4 pb 4 /tp 12 /tocxa 4 pb 4 /tp 12 /tocxa 4 nc 6pb 5 /tp 13 /tocxb 4 pb 5 /tp 13 /tocxb 4 pb 5 /tp 13 /tocxb 4 nc 7pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 nc 8 pb 7 /tp 15 / adtrg pb 7 /tp 15 / adtrg pb 7 /tp 15 / adtrg nc 9p9 0 /txd p9 0 /txd p9 0 /txd nc 10 p9 2 /rxd p9 2 /rxd p9 2 /rxd nc 11 p9 4 /sck/irq 4 p9 4 /sck/irq 4 p9 4 /sck/irq 4 nc 12 v ss v ss v ss v ss 13 d 0 p3 0 p3 0 eo 0 14 d 1 p3 1 p3 1 eo 1 15 d 2 p3 2 p3 2 eo 2 16 d 3 p3 3 p3 3 eo 3 17 d 4 p3 4 p3 4 eo 4 18 d 5 p3 5 p3 5 eo 5 19 d 6 p3 6 p3 6 eo 6 20 d 7 p3 7 p3 7 eo 7 21 v cc v cc v cc v cc 22 p1 0 /a 0 p1 0 p1 0 ea 0 23 p1 1 /a 1 p1 1 p1 1 ea 1 24 p1 2 /a 2 p1 2 p1 2 ea 2 25 p1 3 /a 3 p1 3 p1 3 ea 3 26 p1 4 /a 4 p1 4 p1 4 ea 4 note: pins marked nc should be left unconnected. 7 table 1-2 fp-80a and tfp-80c pin assignments in each mode (cont) pin pin name no. mode 1 mode 2 mode 3 prom mode 27 p1 5 /a 5 p1 5 p1 5 ea 5 28 p1 6 /a 6 p1 6 p1 6 ea 6 29 p1 7 /a 7 p1 7 p1 7 ea 7 30 v ss v ss v ss v ss 31 p2 0 /a 8 p2 0 p2 0 ea 8 32 p2 1 /a 9 p2 1 p2 1 ce 33 p2 2 /a 10 p2 2 p2 2 ea 10 34 p2 3 /a 11 p2 3 p2 3 ea 11 35 p2 4/ a 12 p2 4 p2 4 ea 12 36 p2 5 /a 13 p2 5 p2 5 ea 13 37 p2 6 /a 14 p2 6 p2 6 ea 14 38 p2 7 /a 15 p2 7 p2 7 ce 39 p5 0 /a 16 p5 0 p5 0 v cc 40 p5 1 /a 17 p5 1 p5 1 v cc 41 p5 2 /a 18 p5 2 p5 2 nc 42 p5 3 /a 19 p5 3 p5 3 nc 43 p6 0 / wait p5 4 p5 4 ea 15 44 md 0 md 0 md 0 v ss 45 md 1 md 1 md 1 v ss 46 ? ? ? nc 47 stby stby stby v ss 48 res res res nc 49 nmi nmi nmi ea 9 50 v ss v ss v ss v ss 51 extal extal extal nc 52 xtal xtal xtal nc 53 v cc v cc v cc v cc 8 table 1-2 fp-80a and tfp-80c pin assignments in each mode (cont) pin pin name no. mode 1 mode 2 mode 3 prom mode 54 as p6 3 p6 3 nc 55 rd p6 4 p6 4 nc 56 wr p6 5 p6 5 nc 57 reso reso reso v pp 58 av ss av ss av ss av ss 59 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 nc 60 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 nc 61 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 nc 62 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 nc 63 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 nc 64 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 nc 65 p7 6 /an 6 p7 6 /an 6 p7 6 /an 6 nc 66 p7 7 /an 7 p7 7 /an 7 p7 7 /an 7 nc 67 v ref v ref v ref v cc 68 av cc av cc av cc v cc 69 p8 0 /irq 0 p8 0 /irq 0 p8 0 /irq 0 ea 16 70 p8 1 /irq 1 p8 1 /irq 1 p8 1 /irq 1 pgm 71 p8 2 /irq 2 p8 2 /irq 2 p8 2 /irq 2 nc 72 p8 3 /irq 3 p8 3 /irq 3 p8 3 /irq 3 nc 73 pa 0 /tp 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 /tclka nc 74 pa 1 /tp 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 /tclkb nc 75 pa 2 /tp 2 /tioca 0 /tclkc pa 2 /tp 2 /tioca 0 /tclkc pa 2 /tp 2 /tioca 0 /tclkc nc 76 pa 3 /tp 3 /tiocb 0 /tclkd pa 3 /tp 3 /tiocb 0 /tclkd pa 3 /tp 3 /tiocb 0 /tclkd nc 77 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 /a 23 nc 78 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 /a 22 nc 79 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 /a 21 nc 80 pa 7 /tp 7 /tiocb 2 pa 7 /tp 7 /tiocb 2 pa 7 /tp 7 /tiocb 2 /a 20 nc 9 1.4 pin functions table 1-3 summarizes the pin functions. table 1-3 pin functions type symbol pin no. i/o name and function power v cc 21, 53 input power: for connection to the power supply (+5 v). connect all v cc pins to the +5-v system power supply. v ss 12, 30, 50 input ground: for connection to ground (0 v). connect all v ss pins to the 0-v system power supply. clock xtal 52 input for connection to a crystal resonator. for examples of crystal resonator and external clock input, see section 15, clock pulse generator. extal 51 input for connection to a crystal resonator or input of an external clock signal. for examples of crystal resonator and external clock input, see section 15, clock pulse generator. 46 output system clock: supplies the system clock to external devices operating md 1 , 45, 44 input mode 1 and mode 0: for setting the operating mode control md 0 mode, as follows md 1 md 0 operating mode 00 0 1 mode 1 01 0 mode 2 1 1 mode 3 system control res 48 input reset input: when driven low, this pin resets the h8/3032 reso 57 output reset output: outputs a reset signal to external devices stby 47 input standby: when driven low, this pin forces a transition to hardware standby mode 10 table 1-3 pin functions (cont) type symbol pin no. i/o name and function interrupts nmi 49 input nonmaskable interrupt: requests a nonmaskable interrupt irq 4 to 11, input interrupt request 4 to 0: maskable interrupt irq 0 72 to 69 request pins address bus a 19 to a 8 , 42 to 31, output address bus: outputs address signals a 7 to a 0 29 to 22 data bus d 7 to d 0 20 to 13 input/ data bus: bidirectional data bus output bus control as 54 output address strobe: goes low to indicate valid address output on the address bus rd 55 output read: goes low to indicate reading from the external address space wr 56 output high write: goes low to indicate writing to the external address space; indicates valid data on the data bus. wait 43 input wait: requests insertion of wait states in bus cycles during access to the external address space 16-bit tclkd to 76 to 73 input clock input a to d: external clock inputs integrated tclka time unit tioca 4 to 3, 1, 79, input/ input capture/output compare a4 to a0: (itu) tioca 0 77, 75 output gra4 to gra0 output compare or input capture, or pwm output tiocb 4 to 4, 2, 80, input/ input capture/output compare b4 to b0: tiocb 0 78, 76 output grb4 to grb0 output compare or input capture, or pwm output tocxa 4 5 output output compare xa4: pwm output tocxb 4 6 output output compare xb4: pwm output programmable tp 15 to 8 to 1, output tpc output 15 to 0: pulse output timing pattern tp 0 80 to 73 controller (tpc) 11 table 1-3 pin functions (cont) type symbol pin no. i/o name and function serial com- txd 9 output transmit data: sci data output munication interface (sci) rxd 10 input receive data: sci data input sck 11 input/ serial clock: sci clock input/output output a/d an 7 to an 0 66 to 59 input analog 7 to 0: analog input pins converter adtrg 8 input a/d trigger: external trigger input for starting a/d conversion av cc 68 input power supply pin for the a/d converter. connect to the system power supply (+5 v) when not using the a/d converter. av ss 58 input ground pin for the a/d converter. connect to system ground (0 v) when not using the a/d converter. v ref 67 input reference voltage input pin for the a/d converter. connect to the system power supply (+5 v) when not using the a/d converter. i/o ports p1 7 to p1 0 29 to 22 input/ port 1: eight input/output pins. the direction output of each pin can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 38 to 31 input/ port 2: eight input/output pins. the direction output of each pin can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 20 to 13 input/ port 3: eight input/output pins. the direction output of each pin can be selected in the port 3 data direction register (p3ddr). p5 3 to p5 0 42 to 39 input/ port 5: four input/output pins. the direction of output each pin can be selected in the port 5 data direction register (p5ddr). p6 5 to p6 3 , 56 to 54, input/ port 6: four input/output pins. the direction p6 0 43 output of each pin can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 66 to 59 input port 7: eight input pins p8 3 to p8 0 72 to 69 input/ port 8: four input/output pins. the direction of output each pin can be selected in the port 8 data direction register (p8ddr). 12 table 1-3 pin functions (cont) type symbol pin no. i/o name and function i/o ports p9 4 , p9 2 , 11 to 9 input/ port 9: three input/output pins. the direction p9 0 output of each pin can be selected in the port 9 data direction register (p9ddr). pa 7 to pa 0 80 to 73 input/ port a: eight input/output pins. the direction of output each pin can be selected in the port a data direction register (paddr). pb 7 to pb 0 8 to 1 input/ port b: eight input/output pins. the direction of output each pin can be selected in the port b data direction register (pbddr). 13 14 section 2 cpu 2.1 overview the h8/300h cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 cpu. the h8/300h cpu has sixteen 16-bit general registers, can address a 16-mbyte linear address space, and is ideal for realtime control. 2.1.1 features the h8/300h cpu has the following features. upward compatibility with h8/300 cpu can execute h8/300 series object programs without alteration general-register architecture sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct [rn] register indirect [@ern] register indirect with displacement [@(d:16, ern) or @(d:24, ern)] register indirect with post-increment or pre-decrement [@ern+ or @?rn] absolute address [@aa:8, @aa:16, or @aa:24] immediate [#xx:8, #xx:16, or #xx:32] program-counter relative [@(d:8, pc) or @(d:16, pc)] memory indirect [@@aa:8] 1-mbyte* linear address space note: * the cpu, if used alone, can access a maximum address space of 16 mbytes. however, the maximum address space of the h8/3032 series is 1 mbyte. 15 high-speed operation all frequently-used instructions execute in two to four states maximum clock frequency: 16 mhz 8/16/32-bit register-register add/subtract: 125 ns ? 8-bit register-register multiply: 875 ns 16 8-bit register-register divide: 875 ns 16 16-bit register-register multiply: 1.375 s 32 16-bit register-register divide: 1.375 s two cpu operating modes normal mode advanced mode low-power mode transition to power-down state by sleep instruction 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8/300h has the following enhancements. more general registers eight 16-bit registers have been added. expanded address space advanced mode supports a maximum 1-mbyte address space. normal mode supports the same 64-kbyte address space as the h8/300 cpu. enhanced addressing the addressing modes have been enhanced to make effective use of the 1-mbyte address space. enhanced instructions data transfer, arithmetic, and logic instructions can operate on 32-bit data. signed multiply/divide instructions and other instructions have been added. 16 2.2 cpu operating modes the h8/300h cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports up to 1 mbytes. see figure 2-1. figure 2-1 cpu operating modes cpu operating modes normal mode advanced mode maximum 64 kbytes, program and data areas combined maximum 1 mbyte, program and data areas combined 17 2.3 address space figure 2-2 shows a simple memory map for the h8/3032 series. the h8/300h cpu can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 mbytes in advanced mode. for further details see section 3.6, memory map in each operating mode. the 1-mbyte operating mode uses 20-bit addressing. the upper 4 bits of effective addresses are ignored. figure 2-2 memory map h'00000 h'fffff h'000000 h'ffffff a. 1-mbyte mode b. 16-mbyte mode 18 2.4 register configuration 2.4.1 overview the h8/300h cpu has the internal registers shown in figure 2-3. there are two types of registers: general registers and control registers. figure 2-3 cpu registers er0 er1 er2 er3 er4 er5 er6 er7 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l 0 7 0 7 0 15 (sp) 23 0 pc 7 ccr 6543210 iuihunzvc general registers (ern) control registers (cr) legend sp: pc: ccr: i: ui: h: u: n: z: v: c: stack pointer program counter condition code register interrupt mask bit user bit or interrupt mask bit half-carry flag user bit negative flag zero flag overflow flag carry flag 19 2.4.2 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used without distinction between data registers and address registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or as address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2-4 illustrates the usage of the general registers. the usage of each register can be selected independently. figure 2-4 usage of general registers ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers er0 to er7 e registers (extended registers) e0 to e7 r registers r0 to r7 rh registers r0h to r7h rl registers r0l to r7l 20 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2-5 shows the stack. figure 2-5 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc) and the 8-bit condition code register (ccr). program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant pc bit is ignored. when an instruction is fetched, the least significant pc bit is regarded as 0. condition code register (ccr): this 8-bit register contains internal cpu status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?nterrupt mask bit (i): masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. bit 6?ser bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details see section 5, interrupt controller. free area stack area sp (er7) 21 bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?ser bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?egative flag (n): indicates the most significant bit (sign bit) of data. bit 2?ero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave flag bits unchanged. operations can be performed on ccr by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used by conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a.1, instruction list. for the i and ui bits, see section 5, interrupt controller. 2.4.4 initial cpu register values in reset exception handling, pc is initialized to a value loaded from the vector table, and the i bit in ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer must therefore be initialized by an mov.l instruction executed immediately after a reset. 22 2.5 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ? 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figures 2-6 and 2-7 show the data formats in general registers. figure 2-6 general register data formats (1) 7 rnh rnl rnh rnl rnh rnl 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data 6543210 70 don? care 76543210 70 don? care don? care 70 43 lower digit upper digit 7 43 lower digit upper digit don? care 0 70 don? care msb lsb don? care 70 msb lsb data type data format general register 23 figure 2-7 general register data formats (2) 2.5.2 memory data formats figure 2-8 shows the data formats on memory. the h8/300h cpu can access word data and longword data on memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. rn en ern word data word data longword data 15 0 msb lsb general register data type data format 15 0 msb lsb 31 16 msb 15 0 lsb legend ern: en: rn: rnh: rnl: msb: lsb: general register general register e general register r general register rh general register rl most significant bit least significant bit 24 figure 2-8 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. 76543210 address address lsb msb msb lsb 70 msb lsb 1-bit data byte data word data longword data address data type data format address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 25 2.6 instruction set 2.6.1 instruction set overview the h8/300h cpu has 62 types of instructions, which are classified in table 2-1. table 2-1 instruction classification function instruction types data transfer mov, push * 1 , pop * 1 , movtpe * 2 , movfpe * 2 3 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, 18 mulxu, divxu, mulxs, divxs, cmp, neg, exts, extu logic operations and, or, xor, not 4 shift operations shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, 14 bixor, bld, bild, bst, bist branch bcc * 3 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total 62 types notes: 1. pop.w rn is identical to mov.w @sp+, rn. push.w rn is identical to mov.w rn, @?p. pop.l ern is identical to mov.l @sp+, rn. push.l ern is identical to mov.l rn, @?p. 2. they are not available on h8/3032. 3. bcc is a generic branching instruction. 26 2.6.2 instructions and addressing modes table 2-2 indicates the instructions available in the h8/300h cpu. table 2-2 instructions and addressing modes addressing modes @@ @@ (d:16, (d:24, @ern+/ @ @ @ (d:8, (d:16, @@ function instruction #xx rn @ern ern) ern) @?rn aa:8 aa:16 aa:24 pc) pc) aa:8 implied mov bwl bwl bwl bwl bwl bwl b bwl bwl pop, push wl movfpe, b movtpe add, cmp bwl bwl sub wl bwl addx, subx b b adds, subs l inc, dec bwl daa, das b divxu, bw mulxs, mulxu, divxs neg bwl extu, exts wl logic and, or, bwl bwl operations xor not bwl shift instructions bwl bit manipulation b b b branch bcc, bsr oo jmp, jsr o o o rts o trapa o rte o sleep o ldc b b w w w w w w stc b w w w w w w andc, orc, b xorc nop o block data transfer bw legend b: byte w: word l: longword data transfer arithmetic operations system control 27 2.6.3 tables of instructions classified by function tables 2-3 to 2-10 summarize the instructions in each functional category. the operation notation used in these tables is defined next. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition subtraction multiplication ? division and logical or logical ? exclusive or logical ? move a not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit data or address registers (er0 to er7). 28 table 2-3 data transfer instructions instruction size * function mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) ? rd cannot be used in the h8/3032. movtpe b rs ? (eas) cannot be used in the h8/3032. pop w/l @sp+ ? rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. similarly, pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @esp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @esp. similarly, push.l ern is identical to mov.l ern, @esp. note: * size refers to the operand size. b: byte w: word l: longword 29 table 2-4 arithmetic operation instructions instruction size * function b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from data in a general register. use the subx or add instruction.) b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) l rd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. note: * size refers to the operand size. b: byte w: word l: longword addx, subx inc, dec add, sub adds, subs daa, das 30 table 2-4 arithmetic operation instructions (cont) instruction size * function divxu b/w rd rs ? rd performs unsigned division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. divxs b/w rd ? rs ? rd performs signed division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder, or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. cmp b/w/l rd e rs, rd e #imm compares data in a general register with data in another general register or with immediate data, and sets ccr according to the result. neg b/w/l 0 e rd ? rd takes the two?s complement (arithmetic complement) of data in a general register. exts w/l rd (sign extension) ? rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. extu w/l rd (zero extension) ? rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. note: * size refers to the operand size. b: byte w: word l: longword 31 table 2-5 logic operation instructions instruction size * function and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l a rd ? rd takes the one?s complement of general register contents. note: * size refers to the operand size. b: byte w: word l: longword table 2-6 shift instructions instruction size * function b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. b/w/l rd (shift) ? rd performs a logical shift on general register contents. b/w/l rd (rotate) ? rd rotates general register contents. b/w/l rd (rotate) ? rd rotates general register contents through the carry bit. note: * size refers to the operand size. b: byte w: word l: longword shal, shar shll, shlr rotl, rotr rotxl, rotxr 32 table 2-7 bit manipulation instructions instruction size * function bset b 1 ? ( table 2-7 bit manipulation instructions (cont) instruction size * function bor b c ( table 2-8 branching instructions instruction size function bcc branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine 35 table 2-9 system control instructions instruction size * function trapa starts trap-instruction exception handling rte returns from an exception-handling routine sleep causes a transition to the power-down state ldc b/w (eas) ? ccr moves the source operand contents to the condition code register. the condition code register size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr ? (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ? ccr logically ands the condition code register with immediate data. orc b ccr #imm ? ccr logically ors the condition code register with immediate data. xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data. nop ? pc + 2 ? pc only increments the program counter. note: * size refers to the operand size. b: byte w: word 36 table 2-10 block transfer instruction instruction size function eepmov.b if r4l 0 then repeat @er5+ ? @er6+, r4l e 1 ? r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ ? @er6+, r4 e 1 ? r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. 37 2.6.4 basic instruction formats the h8/300h instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first 4 bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (h'00). condition field: specifies the branching condition of bcc instructions. figure 2-9 shows examples of instruction formats. figure 2-9 instruction formats op nop, rts, etc. op rn rm op rn rm ea (disp) operation field only add.b rn, rm, etc. operation field and register fields mov.b @(d:16, rn), r m operation field, register fields, and effective address extension bra d:8 operation field, effective address extension, and condition field op cc ea (disp) 38 2.6.5 notes on use of bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, modify a bit in the byte, then write the byte back. care is required when these instructions are used to access registers with write-only bits, or to access ports. the bclr instruction can be used to clear flags in the on-chip registers. in an interrupt-handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. 2.7 addressing modes and effective address calculation 2.7.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2-11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2-11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16, ern)/@d:24, ern) 4 register indirect with post-increment @ern+ register indirect with pre-decrement @?rn 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 39 1 register direct?n: the register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2 register indirect?ern: the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand. 3 register indirect with displacement?(d:16, ern) or @(d:24, ern): a 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. a 16-bit displacement is sign-extended when added. 4 register indirect with post-increment or pre-decrement?ern+ or @?rn: register indirect with post-increment?ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contain the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. register indirect with pre-decrement??rn the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the resulting register value should be even. 5 absolute address?aa:8, @aa:16, or @aa:24: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign extension. a 24-bit absolute address can access the entire address space. table 2-12 indicates the accessible address ranges. 40 table 2-12 absolute address access ranges absolute address 1-mbyte modes 64-kbyte modes 8 bits (@aa:8) h'fff00 to h'fffff h'ff00 to h'ffff (1048320 to 1048575) (65280 to 65535) 16 bits (@aa:16) h'00000 to h'07fff, h'0000 to h'ffff h'f8000 to h'fffff (0 to 65535) (0 to 32767, 1015808 to 1048575) 24 bits (@aa:24) h'00000 to h'fffff h'000000 to h'00ffff (0 to 1048575) (0 to 65535) 6 immediate?xx:8, #xx:16, or #xx:32: the instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the instruction codes of the adds, subs, inc, and dec instructions contain immediate data implicitly. the instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. the trapa instruction code contains 2-bit immediate data specifying a vector address. 7 program-counter relative?(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit pc contents to generate a 24-bit branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?26 to +128 bytes (?3 to +64 words) or ?2766 to +32768 bytes (?6383 to +16384 words) from the branch instruction. the resulting value should be an even number. 8 memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byte of the memory operand is ignored, generating a 24-bit branch address. see figure 2-10. the upper bits of the 8-bit absolute address are assumed to be 0 (h'0000), so the address range is 0 to 255 (h'000000 to h'0000ff). note that the first part of this range is also the exception vector area. for further details see section 5, interrupt controller. 41 figure 2-10 memory-indirect branch address specification when a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. the accessed data or instruction code therefore begins at the preceding address. see section 2.5.2, memory data formats. 2.7.2 effective address calculation table 2-13 explains how an effective address is calculated in each addressing mode. in the 1-mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. specified by @aa:8 reserved branch address 42 table 2-13 effective address calculation addressing mode and instruction format no. effective address calculation effective address register direct (rn) 1 operand is general register contents op rm rn register indirect (@ern) 2 op r general register contents 31 0 23 0 register indirect with displacement @(d:16, ern)/@(d:24, ern) 3 op r general register contents 31 0 23 0 disp sign extension disp register indirect with post-increment or pre-decrement 4 general register contents 31 0 23 0 1, 2, or 4 op r general register contents 31 0 23 0 1, 2, or 4 op r 1 for a byte operand, 2 for a word operand, 4 for a longword operand register indirect with post-increment @ern+ register indirect with pre-decrement @?rn 43 table 2-13 effective address calculation (cont) addressing mode and instruction format no. effective address calculation effective address absolute address @aa:8 5 op program-counter relative @(d:8, pc) or @(d:16, pc) 7 0 23 0 abs 23 0 87 @aa:16 op abs 23 0 16 15 h'ffff sign extension @aa:24 op 23 0 abs immediate #xx:8, #xx:16, or #xx:32 6 operand is immediate data op disp 23 0 pc contents disp op imm sign extension 44 table 2-13 effective address calculation (cont) addressing mode and instruction format no. effective address calculation effective address memory indirect @@aa:8 8 op 23 0 abs 23 0 87 h'0000 memory contents 31 0 abs legend r, rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address advanced mode op 23 0 abs 23 0 87 h'0000 15 0 abs normal mode 16 15 h'00 memory contents 45 2.8 processing states 2.8.1 overview the h8/300h cpu has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. the power-down state includes sleep mode, software standby mode, and hardware standby mode. figure 2-11 classifies the processing states. figure 2-13 indicates the state transitions. figure 2-11 processing states processing states program execution state reset state power-down state the cpu executes program instructions in sequence a transient state in which the cpu executes a hardware sequence (saving pc and ccr, fetching a vector, etc.) in response to a reset, interrupt, or other exception the cpu and all on-chip supporting modules are initialized and halted the cpu is halted to conserve power sleep mode software standby mode hardware standby mode exception-handling state 46 2.8.2 program execution state in this state the cpu executes program instructions in normal sequence. 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal program flow due to a reset, interrupt, or trap instruction. the cpu fetches a starting address from the exception vector table and branches to that address. in interrupt and trap exception handling the cpu references the stack pointer (er7) and saves the program counter and condition code register. types of exception handling and their priority: exception handling is performed for resets, interrupts, and trap instructions. table 2-14 indicates the types of exception handling and their priority. trap instruction exceptions are accepted at all times in the program execution state. table 2-14 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately when res changes from low to high interrupt end of instruction when an interrupt is requested, execution or end of exception handling starts at the end of exception handling * the current instruction or current exception-handling sequence trap instruction when trapa instruction exception handling starts when a trap low is executed (trapa) instruction is executed note: * interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. figure 2-12 classifies the exception sources. for further details about exception sources, vector numbers, and vector addresses, see section 4, exception handling, and section 5, interrupt controller. 47 figure 2-12 classification of exception sources figure 2-13 state transitions exception sources reset interrupt trap instruction external interrupts internal interrupts (from on-chip supporting modules) exception-handling state reset state program execution state sleep mode software standby mode hardware standby mode power-down state end of exception handling exception interrupt sleep instruction with ssby = 0 sleep instruction with ssby = 1 nmi, irq , irq , or irq interrupt stby res = 1, = 0 res = 1 01 2 * 1 * 2 notes: 1. 2. from any state except hardware standby mode, a transition to the reset state occurs whenever goes low. from any state, a transition to hardware standby mode occurs when goes low. res stby 48 2.8.4 exception-handling sequences reset exception handling: reset exception handling has the highest priority. the reset state is entered when the res signal goes low. reset exception handling starts after that, when res changes from low to high. when reset exception handling starts the cpu fetches a start address from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during the reset exception-handling sequence and immediately after it ends. interrupt exception handling and trap instruction exception handling: when these exception-handling sequences begin, the cpu references the stack pointer (er7) and pushes the program counter and condition code register on the stack. next, if the ue bit in the system control register (syscr) is set to 1, the cpu sets the i bit in the condition code register to 1. if the ue bit is cleared to 0, the cpu sets both the i bit and the ui bit in the condition code register to 1. then the cpu fetches a start address from the exception vector table and execution branches to that address. figure 2-14 shows the stack after the exception-handling sequence. figure 2-14 stack structure after exception handling sp? sp? sp? sp? sp (er7) before exception handling starts sp (er7) sp+1 sp+2 sp+3 sp+4 after exception handling ends stack area ccr pc even address pushed on stack legend ccr: sp: condition code register stack pointer notes: 1. 2. pc is the address of the first instruction executed after the return from the exception-handling routine. registers must be saved and restored by word access or longword access, starting at an even address. 49 2.8.5 reset state when the res input goes low all current processing stops and the cpu enters the reset state. the i bit in the condition code register is set to 1 by a reset. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details see section 10, watchdog timer. 2.8.6 power-down state in the power-down state the cpu stops operating to conserve power. there are three modes: sleep mode, software standby mode, and hardware standby mode. sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit is cleared to 0 in the system control register (syscr). cpu operations stop immediately after execution of the sleep instruction, but the contents of cpu registers are retained. software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit is set to 1 in syscr. the cpu and clock halt and all on-chip supporting modules stop operating. the on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. hardware standby mode: a transition to hardware standby mode is made when the stby input goes low. as in software standby mode, the cpu and clock halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. for further information see section 16, power-down state. 50 2.9 basic operational timing 2.9.1 overview the h8/300h cpu operates according to the system clock (?. the interval from one rise of the system clock to the next rise is referred to as a ?tate.? a memory cycle or bus cycle consists of two or three states. the cpu uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. access to the external address space can be controlled by the bus controller. 2.9.2 on-chip memory access timing on-chip memory is accessed in two states. the data bus is 16 bits wide, permitting both byte and word access. figure 2-15 shows the on-chip memory access cycle. figure 2-16 indicates the pin states. figure 2-15 on-chip memory access cycle t state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal internal data bus (write access) 1 t state 2 read data address write data 51 figure 2-16 pin states during on-chip memory access t , , as 1 t 2 address bus d 7 to d 0 rd wr high address high impedance 52 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in three states. the data bus is 8 or 16 bits wide, depending on the register being accessed. figure 2-17 shows the on-chip supporting module access timing. figure 2-18 indicates the pin states. figure 2-17 access cycle for on-chip supporting modules address bus internal read signal internal data bus internal write signal address internal data bus t state bus cycle 1 t state 2 t state 3 read access write access write data read data 53 figure 2-18 pin states during access to on-chip supporting modules 2.9.4 access to external address space the external address space is divided into eight areas (areas 0 to 7). bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states. for details see section 6, bus controller. address t , , , as 1 t 2 address bus d 7 to d 0 rd hwr lwr high high impedance t 3 54 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8/3032 series has three operating modes (modes 1 to 3) that are selected by the mode pins (md 1 and md 0 ) as indicated in table 3-1. the input at these pins determines expanded mode or single-chip mode. table 3-1 operating mode selection mode pins description operating mode md 1 md 0 address space initial bus width * 1 on-chip ram ?0 mode 1 0 1 1 mbyte 8 bits enabled * 1 mode 2 1 0 64 kbytes enabled * 2 mode 3 1 1 1 mbyte enabled * 2 notes: 1. in mode 1, if the ram enable bit (rame) in the system control register (syscr) is cleared to 0, these addresses become external addresses. 2. in modes 2 and 3, clearing bit rame of syscr to 0 and reading the on-chip ram always returns h?f, and write access is ignored. for details, see section 13.3, operation. for the address space size there are two choices: 64 kbytes or 1 mbyte. modes 1 and 3 support a maximum address space of 1 mbyte. mode 2 supports a maximum address space of 64 kbytes. the h8/3032 series can only be used in modes 1 to 3. the inputs at the mode pins must select one of these three modes. the inputs at the mode pins must not be changed during operation. 55 3.1.2 register configuration the h8/3032 series has a mode control register (mdcr) that indicates the inputs at the mode pins (md 2 to md 0 ), and a system control register (syscr). table 3-2 summarizes these registers. table 3-2 registers address * name abbreviation r/w initial value h'fff1 mode control register mdcr r undetermined h'fff2 system control register syscr r/w h'0b note: * the lower 16 bits of the address are indicated. 56 3.2 mode control register (mdcr) mdcr is an 8-bit read-only register that indicates the current operating mode of the h8/3032 series. bits 7 and 6?eserved: read-only bits, always read as 1. bits 5 to 3?eserved: read-only bits, always read as 0. bit 2?eserved: read-only bit, always read as 1. bits 1 and 0?ode select 1 and 0 (mds1 and mds0): these bits indicate the logic levels at pins md 1 and md 0 (the current operating mode). mds1 and mds0 correspond to md 1 and md 0 . mds1 and mds0 are read-only bits. the mode pin (md 1 and md 0 ) levels are latched when mdcr is read. bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 4 ? 0 3 ? 0 0 mds0 ? r 2 ? 1 1 mds1 ? r * * mode select 1 and 0 bits indicating the current operating mode reserved bits note: determined by pins md and md . * 10 57 3.3 system control register (syscr) syscr is an 8-bit register that controls the operation of the h8/3032 series. bit 7?oftware standby (ssby): enables transition to software standby mode. (for further information about software standby mode see section 16, power-down state.) when software standby mode is exited by an external interrupt, this bit remains set to 1. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 1 software standby enables transition to software standby mode user bit enable selects whether to use ui bit in ccr 6 as a user bit or an interrupt mask bit nmi edge select selects the valid edge of the nmi input reserved bit ram enable enables or disables on-chip ram standby timer select 2 to 0 these bits select the waiting time at recovery from software standby mode 58 bits 6 to 4?tandby timer select (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. set these bits so that the waiting time will be at least 8 ms at the system clock rate. for further information about waiting time selection, see section 19.4.3, selection of oscillator waiting time after exit from software standby mode. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 000w aiting time = 8192 states (initial value) 001w aiting time = 16384 states 010w aiting time = 32768 states 011w aiting time = 65536 states 1 0 waiting time = 131072 states 1 1 illegal setting bit 3?ser bit enable (ue): selects whether to use the ui bit in the condition code register as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as an interrupt mask bit 1 ui bit in ccr is used as a user bit (initial value) bit 2?mi edge select (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested at the falling edge of nmi (initial value) 1 an interrupt is requested at the rising edge of nmi bit 1?eserved: read-only bit, always read as 1. bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized by the rising edge of the res signal. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 59 3.4 operating mode descriptions 3.4.1 mode 1 1-mbyte address space can be accessed including the on-chip rom addresses. port 3 pins function as data pins d 7 to d 0 and port 1, 2, and 5 pins function as address pins a 19 to a 0 . the address bus width can be selected by setting ddr of ports 1, 2, and 5. 3.4.2 mode 2 this mode is a normal mode with a 64-kbyte address space which operates using the on-chip rom, ram, and registers. external addresses cannot be accessed. the vector area and stack area can be saved. 3.4.3 mode 3 this mode is an advanced mode with a 1-mbyte address space which operates using the on-chip rom, ram, and registers. external addresses cannot be accessed. 60 3.5 pin functions in each operating mode the pin functions of ports 1, 2, 3, 5, and 6 vary depending on the operating mode. table 3-3 indicates their functions in each operating mode. table 3-3 pin functions in each mode port mode 1 modes 2, 3 port 1 p1 7 to p1 0 * 1 p1 7 to p1 0 port 2 p2 7 to p2 0 * 1 p2 7 to p2 0 port 3 d 7 to d 0 p3 7 to p3 0 port 5 p5 3 to p5 0 * 1 p5 3 to p5 0 port 6 wr , rd , as , p6 6 / wait * 2 p6 5 to p6 3 , p6 0 notes: 1. initial state. these pins function as an address bus by setting the corresponding ddr bit to 1. 2. the functions of these pins vary depending on the settings in the wait state controller enable register (wcer), wait control register (wcr), and port data direction register. 3.6 memory map in each operating mode figure 3-1 shows a memory map of the h8/3032. figure 3-2 shows a memory map of the h8/3031. figure 3-3 shows a memory map of the h8/3030. the address space is divided into eight areas. 61 figure 3-1 h8/3032 memory map in each operating mode 16-bit absolute addresses (first half) 8-bit memory- indirect addresses 16-bit absolute addresses (second half) 8-bit absolute addresses vector table on-chip rom area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external addresses on-chip ram * external addresses on-chip register h'00000 h'000ff h'07fff h'0ffff h'10000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 h'f8000 h'ff70f h'ff710 h'fff00 h'fff0f h'fff10 h'fff1b h'fff1c h'fffff mode 1 (expanded mode with on-chip rom) mode 2 (single-chip normal mode) mode 3 (single-chip advanced mode) vector table on-chip rom h'0000 h'00ff h'f70f on-chip ram on-chip registers h'f710 h'ff00 h'ff0f h'ff1c h'ffff 8-bit absolute addresses vector table on-chip rom h'00000 h'000ff h'07fff 16-bit absolute addresses (first half) 16-bit absolute addresses (second half) 8-bit absolute addresses h'f8000 h'ff710 h'fff00 h'fff0f h'fff1c h'fffff on-chip ram on-chip registers 8-bit memory- indirect addresses 8-bit memory- indirect addresses h'0ffff note: * external addresses can be accessed by disabling on-chip ram. 62 figure 3-2 h8/3031 memory map in each operating mode 63 16-bit absolute addresses (first half) 8-bit memory- indirect addresses 16-bit absolute addresses (second half) 8-bit absolute addresses vector table on-chip rom reserved area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external addresses reserved on-chip ram * 1 external addresses on-chip register h'00000 h'000ff h'07fff h'0ffff h'10000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 h'f8000 h'ff710 h'ffb0f h'ffb10 h'fff00 h'fff0f h'fff10 h'fff1b h'fff1c h'fffff mode 1 (expanded mode with on-chip rom) mode 2 (single-chip normal mode) mode 3 (single-chip advanced mode) vector table on-chip rom h'0000 h'00ff h'7fff on-chip ram on-chip registers h'fb10 h'ff00 h'ff0f h'ff1c h'ffff 8-bit absolute addresses vector table on-chip rom h'00000 h'000ff h'07fff 16-bit absolute addresses (first half) 16-bit absolute addresses (second half) 8-bit absolute addresses h'f8000 h'ffb10 h'fff00 h'fff0f h'fff1c h'fffff on-chip ram on-chip registers 8-bit memory- indirect addresses 8-bit memory- indirect addresses notes: 1. 2. external addresses can be accessed by disabling on-chip rom. do not accessed reserved areas. figure 3-3 h8/3030 memory map in each operating mode 64 16-bit absolute addresses (first half) 8-bit memory- indirect addresses 16-bit absolute addresses (second half) 8-bit absolute addresses vector table on-chip rom reserved area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external addresses reserved on-chip ram * 1 external addresses on-chip register h'00000 h'000ff h'03fff h'0ffff h'10000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 h'f8000 h'ff710 h'ffd0f h'ffd10 h'fff00 h'fff0f h'fff10 h'fff1b h'fff1c h'fffff mode 1 (with on-chip rom) mode 2 (single-chip normal mode) mode 3 (single-chip advanced mode) vector table on-chip rom h'0000 h'00ff h'3fff on-chip ram on-chip registers h'fd10 h'ff00 h'ff0f h'ff1c h'ffff 8-bit absolute addresses vector table on-chip rom h'00000 h'000ff h'03fff 16-bit absolute addresses (first half) 16-bit absolute addresses (second half) 8-bit absolute addresses h'f8000 h'ffd10 h'fff00 h'fff0f h'fff1c h'fffff on-chip ram on-chip registers 8-bit memory- indirect addresses 8-bit memory- indirect addresses notes: 1. 2. external addresses can be accessed by disabling on-chip rom. do not accessed reserved areas. section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 4-1. if two or more exceptions occur simultaneously, they are accepted and processed in priority order. trap instruction exceptions are accepted at all times in the program execution state. table 4-1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin interrupt interrupt requests are handled when execution of the current instruction or handling of the current exception is completed low trap instruction (trapa) started by execution of a trap instruction (trapa) 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows. 1. the program counter (pc) and condition code register (ccr) are pushed onto the stack. 2. the ccr interrupt mask bit is set to 1. 3. a vector address corresponding to the exception source is generated, and program execution starts from the address indicated in the vector address. for a reset exception, steps 2 and 3 above are carried out. 65 4.1.3 exception vector table the exception sources are classified as shown in figure 4-1. different vectors are assigned to different exception sources. table 4-2 lists the exception sources and their vector addresses. figure 4-1 exception sources table 4-2 exception vector table vector address * 1 exception source vector number advanced mode normal mode reset 0 h'0000 to h'0003 h'0000 to h'0001 reserved for system use 1 h'0004 to h'0007 h'0002 to h'0003 2 h'0008 to h'000b h'0004 to h'0005 3 h'000c to h'000f h'0006 to h'0007 4 h'0010 to h'0013 h'0008 to h'0009 5 h'0014 to h'0017 h'000a to h'000b 6 h'0018 to h'001b h'000c to h'000d external interrupt (nmi) 7 h'001c to h'001f h'000e to h'000f trap instruction (4 sources) 8 h'0020 to h'0023 h'0010 to h'0011 9 h'0024 to h'0027 h'0012 to h'0013 10 h'0028 to h'002b h'0014 to h'0015 11 h'002c to h'002f h'0016 to h'0017 external interrupt irq 0 12 h'0030 to h'0033 h'0018 to h'0019 irq 1 13 h'0034 to h'0037 h'001a to h'001b irq 2 14 h'0038 to h'003b h'001c to h'001d irq 3 15 h'003c to h'003f h'001e to h'001f irq 4 16 h'0040 to h'0043 h'0020 to h'0021 reserved for system use 17 h'0044 to h'0047 h'0022 to h'0023 18 h'0048 to h'004b h'0024 to h'0025 19 h'004c to h'004f h'0026 to h'0027 internal interrupts * 2 20 h'0050 to h'0053 h'0028 to h'0029 to to 60 h'00f0 to h'00f3 h'0078 to h'0079 notes: 1. lower 16 bits of the address. 2. for the internal interrupt vectors, see section 5.3.3, interrupt vector table. exception sources ? reset ? interrupts ? trap instruction external interrupts: internal interrupts: nmi, irq to irq 21 interrupts from on-chip supporting modules 0 4 66 4.2 reset 4.2.1 overview a reset is the highest-priority exception. when the res pin goes low, all processing halts and the h8/3032 series enters the reset state. a reset initializes the internal state of the cpu and the registers of the on-chip supporting modules. reset exception handling begins when the res pin changes from low to high. the h8/3032 series can also be reset by overflow of the watchdog timer. for details see section 10, watchdog timer. 4.2.2 reset sequence the h8/3032 series enters the reset state when the res pin goes low. to ensure that the h8/3032 series is reset, hold the res pin low for at least 20 ms at power-up. to reset the h8/3032 series during operation, hold the res pin low for at least 10 system clock (? cycles. see appendix d.2, pin states at reset, for the states of the pins in the reset state. when the res pin goes high after being held low for the necessary time, the h8/3032 series starts reset exception handling as follows. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. the contents of the reset vector address (h'0000 to h'0003 in advanced mode, h'0000 to h'0001 in normal mode) are read, and program execution starts from the address indicated in the vector address. figure 4-2 shows the reset sequence in modes 1 and 3. figure 4-3 shows the reset sequence in mode 2. 67 figure 4-2 reset sequence (modes 1 and 3) (2) (4) (6) (5) (3) (1) res address bus internal read signal internal write signal on chip data vector fetch internal processing prefetch of first program instruction (1), (3) (2), (4) (5) (6) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. address of reset vector: (1) = h'00000, (3) = h'00002 start address (contents of reset vector) start address first instruction of program 68 figure 4-3 reset sequence (mode 2) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. the first instruction of the program is always executed immediately after the reset state ends. this instruction should initialize the stack pointer (example: mov.l #xx:32, sp). address bus res rd wr d to d 15 0 vector fetch internal processing prefetch of first program instruction (1), (3) (2), (4) (5) (6) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. high address of reset vector: (1) = h'00000, (3) = h'00002 start address (contents of reset vector) start address first instruction of program (2) (4) (3) (1) (5) (6) 69 4.3 interrupts interrupt exception handling can be requested by nine external sources (nmi, irq 0 to irq 4 ) and 21 internal sources in the on-chip supporting modules. figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. the on-chip supporting modules that can request interrupts are the watchdog timer (wdt), 16-bit integrated timer unit (itu), serial communication interface (sci), and a/d converter. each interrupt source has a separate vector address. nmi is the highest-priority interrupt and is always accepted. interrupts are controlled by the interrupt controller. the interrupt controller can assign interrupts other than nmi to two priority levels, and arbitrate between simultaneous interrupts. interrupt priorities are assigned in interrupt priority registers a and b (ipra and iprb) in the interrupt controller. for details on interrupts see section 5, interrupt controller. figure 4-4 interrupt sources and number of interrupts interrupts external interrupts internal interrupts nmi (1) irq to irq (5) wdt * (1) itu (15) sci (4) a/d converter (1) note: numbers in parentheses are the number of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. 0 4 70 4.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. if the ue bit is set to 1 in the system control register (syscr), the exception handling sequence sets the i bit to 1 in ccr. if the ue bit is 0, the i and ui bits are both set to 1. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 71 4.5 stack status after exception handling figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. figure 4-5 stack after completion of exception handling 72 sp-4 sp-3 sp-2 sp-1 sp (er7) ? sp (er7) sp+1 sp+2 sp+3 sp+4 ? sp-4 sp-3 sp-2 sp-1 sp (er7) ? sp (er7) sp+1 sp+2 sp+3 sp+4 ? before exception handling before exception handling after exception handling ccr ccr pc pc ccr pc pc pc h l e h l * after exception handling even address even address save on stack save on stack a. normal mode b. advanced mode legend pce: pch: pcl: ccr: sp: notes: this is the address of the first instruction executed after return. saving and restoring of registers must be conducted at even addresses in word-size or longword-size units. ignored upon return. 1. 2. * bits 23 to 16 of program counter (pc) bits 15 to 8 of program counter (pc) bits 7 to 0 of program counter (pc) condition code register stack pointer stack area stack area 4.6 notes on stack usage when accessing word data or longword data, the h8/3032 series regards the lowest address bit as 0. the stack should always be accessed by word access or longword access, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @?p) push.l ern (or mov.l ern, @?p) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4-6 shows an example of what happens when the sp value is odd. figure 4-6 operation when sp value is odd 73 trapa instruction executed ccr legend ccr: pc: r1l: sp: sp pc ril pc sp sp mov. b ril, @-er7 sp set to h'fffeff data saved above sp ccr contents lost condition code register program counter general register r1l stack pointer note: the diagram illustrates modes 1 and 3. h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff 74 section 5 interrupt controller 5.1 overview 5.1.1 features the interrupt controller has the following features: interrupt priority registers (iprs) for setting interrupt priorities interrupts other than nmi can be assigned to two priority levels on a module-by-module basis in interrupt priority registers a and b (ipra and iprb). three-level masking by the i and ui bits in the cpu condition code register (ccr) independent vector addresses all interrupts are independently vectored; the interrupt service routine does not have to identify the interrupt source. six external interrupt pins nmi has the highest priority and is always accepted; either the rising or falling edge can be selected. for each of irq 0 to irq 4 , sensing of the falling edge or level sensing can be selected independently. 75 5.1.2 block diagram figure 5-1 shows a block diagram of the interrupt controller. figure 5-1 interrupt controller block diagram iscr ier ipra, iprb . . . ovf tme adi adie . . . . . . . cpu ccr i ui ue syscr i: ier: ipra: iprb: iscr: isr: syscr: ue: ui: nmi input irq input irq input section isr interrupt controller priority decision logic interrupt request vector number interrupt mask bit irq enable register interrupt priority register a interrupt priority register b irq sense control register irq status register system control register user bit enable user bit/interrupt mask bit legend 76 5.1.3 pin configuration table 5-1 lists the interrupt pins. table 5-1 interrupt pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable interrupt, rising edge or falling edge selectable external interrupt request 4 to 0 irq 4 to irq 0 input maskable interrupts, falling edge or level sensing selectable 5.1.4 register configuration table 5-2 lists the registers of the interrupt controller. table 5-2 interrupt controller registers address * 1 name abbreviation r/w initial value h'fff2 system control register syscr r/w h'0b h'fff4 irq sense control register iscr r/w h'00 h'fff5 irq enable register ier r/w h'00 h'fff6 irq status register isr r/(w) * 2 h'00 h'fff8 interrupt priority register a ipra r/w h'00 h'fff9 interrupt priority register b iprb r/w h'00 notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear flags. 77 5.2 register descriptions 5.2.1 system control register (syscr) syscr is an 8-bit readable/writable register that controls software standby mode, selects the action of the ui bit in ccr, selects the nmi edge, and enables or disables the on-chip ram. only bits 3 and 2 are described here. for the other bits, see section 3.3, system control register (syscr). syscr is initialized to h'0b by a reset and in hardware standby mode. it is not initialized in software standby mode. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 1 r/w software standby standby timer select 2 to 0 user bit enable selects whether to use ccr bit 6 as a user bit or interrupt mask bit nmi edge select selects the nmi input edge reserved bit ram enable 78 bit 3?ser bit enable (ue): selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as interrupt mask bit 1 ui bit in ccr is used as user bit (initial value) bit 2?mi edge select (nmieg): selects the nmi input edge. bit 2 nmieg description 0 interrupt is requested at falling edge of nmi input (initial value) 1 interrupt is requested at rising edge of nmi input 5.2.2 interrupt priority registers a and b (ipra, iprb) ipra and iprb are 8-bit readable/writable registers that control interrupt priority. 79 interrupt priority register a (ipra): ipra is an 8-bit readable/writable register in which interrupt priority levels can be set. ipra is initialized to h'00 by a reset and in hardware standby mode. bit initial value read/write 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 0 ipra0 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w priority level a7 selects the priority level of irq interrupt requests priority level a3 selects the priority level of wdt interrupt requests priority level a2 selects the priority level of itu channel 0 interrupt requests priority level a1 selects the priority level of itu channel 1 interrupt requests priority level a0 selects the priority level of itu channel 2 interrupt requests selects the priority level of irq interrupt requests priority level a6 selects the priority level of irq and irq interrupt requests priority level a5 selects the priority level of irq interrupt requests priority level a4 0 1 23 4 80 bit 7?riority level a7 (ipra7): selects the priority level of irq 0 interrupt requests. bit 7 ipra7 description 0 irq 0 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 0 interrupt requests have priority level 1 (high priority) bit 6?riority level a6 (ipra6): selects the priority level of irq 1 interrupt requests. bit 6 ipra6 description 0 irq 1 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 1 interrupt requests have priority level 1 (high priority) bit 5?riority level a5 (ipra5): selects the priority level of irq 2 and irq 3 interrupt requests. bit 5 ipra5 description 0 irq 2 and irq 3 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 2 and irq 3 interrupt requests have priority level 1 (high priority) bit 4?riority level a4 (ipra4): selects the priority level of irq 4 interrupt requests. bit 4 ipra4 description 0 irq 4 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 4 interrupt requests have priority level 1 (high priority) 81 bit 3?riority level a3 (ipra3): selects the priority level of wdt interrupt requests. bit 3 ipra3 description 0 wdt interrupt requests have priority level 0 (low priority) (initial value) 1 wdt interrupt requests have priority level 1 (high priority) bit 2?riority level a2 (ipra2): selects the priority level of itu channel 0 interrupt requests. bit 2 ipra2 description 0 itu channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 itu channel 0 interrupt requests have priority level 1 (high priority) bit 1?riority level a1 (ipra1): selects the priority level of itu channel 1 interrupt requests. bit 1 ipra1 description 0 itu channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 itu channel 1 interrupt requests have priority level 1 (high priority) bit 0?riority level a0 (ipra0): selects the priority level of itu channel 2 interrupt requests. bit 0 ipra0 description 0 itu channel 2 interrupt requests have priority level 0 (low priority) (initial value) 1 itu channel 2 interrupt requests have priority level 1 (high priority) 82 interrupt priority register b (iprb): iprb is an 8-bit readable/writable register in which interrupt priority levels can be set. iprb is initialized to h'00 by a reset and in hardware standby mode. bit initial value read/write 7 iprb7 0 r/w 6 iprb6 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 iprb3 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 iprb1 0 r/w priority level b7 selects the priority level of itu channel 3 interrupt requests priority level b3 selects the priority level of sci channel 0 interrupt requests reserved bit priority level b1 selects the priority level of a/d converter interrupt request reserved bit selects the priority level of itu channel 4 interrupt requests priority level b6 reserved bits 83 bit 7?riority level b7 (iprb7): selects the priority level of itu channel 3 interrupt requests. bit 7 iprb7 description 0 itu channel 3 interrupt requests have priority level 0 (low priority) (initial value) 1 itu channel 3 interrupt requests have priority level 1 (high priority) bit 6?riority level b6 (iprb6): selects the priority level of itu channel 4 interrupt requests. bit 6 iprb6 description 0 itu channel 4 interrupt requests have priority level 0 (low priority) (initial value) 1 itu channel 4 interrupt requests have priority level 1 (high priority) bits 5 and 4?eserved: these bits can be written and read, but it does not affect interrupt priority. bit 3?riority level b3 (iprb3): selects the priority level of sci interrupt requests. bit 3 iprb3 description 0 sci interrupt requests have priority level 0 (low priority) (initial value) 1 sci interrupt requests have priority level 1 (high priority) bit 2?eserved: this bit can be written and read, but it does not affect interrupt priority. bit 1?riority level b1 (iprb1): selects the priority level of a/d converter interrupt requests. bit 1 iprb1 description 0 a/d converter interrupt requests have priority level 0 (low priority) (initial value) 1 a/d converter interrupt requests have priority level 1 (high priority) bit 0?eserved: this bit can be written and read, but it does not affect interrupt priority. 84 5.2.3 irq status register (isr) isr is an 8-bit readable/writable register that indicates the status of irq 0 to irq 4 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 5?eserved: read-only bits, always read as 0. bits 4 to 0?rq 4 to irq 0 flags (irq4f to irq0f): these bits indicate the status of irq 4 to irq 0 interrupt requests. bits 4 to 0 irq4f to irq0f description 0 [clearing conditions] (initial value) 0 is written in irqnf after reading the irqnf flag when irqnf = 1. irqnsc = 0, irqn input is high, and interrupt exception handling is carried out. irqnsc = 1 and irqn interrupt exception handling is carried out. 1 [setting conditions] irqnsc = 0 and irqn input is low. irqnsc = 1 and irqn input changes from high to low. note: n = 4 to 0 bit initial value read/write 7 ? 0 r/(w) these bits indicate irq 4 to irq 0 interrupt request status note: only 0 can be written, to clear flags. * * 6 ? 0 r/(w) * 5 ? 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * irq to irq flags 40 reserved bits 85 5.2.4 irq enable register (ier) ier is an 8-bit readable/writable register that enables or disables irq 0 to irq 4 interrupt requests. ier is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 5?eserved: these bits can be written and read, but they do not enable or disable interrupts. bits 4 to 0?rq 4 to irq 0 enable (irq7e to irq0e): these bits enable or disable irq 4 to irq 0 interrupts. bits 4 to 0 irq4e to irq0e description 0 irq 4 to irq 0 interrupts are disabled (initial value) 1 irq 4 to irq 0 interrupts are enabled bit initial value read/write 7 ? 0 r/w these bits enable or disable irq 4 to irq 0 interrupts 6 ? 0 r/w 5 ? 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w irq to irq enable 40 reserved bits 86 5.2.5 irq sense control register (iscr) iscr is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins irq 4 to irq 0 . iscr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 5?eserved: these bits can be written and read, but they do not select level or falling- edge sensing. bits 4 to 0?rq 4 to irq 0 sense control (irq4sc to irq0sc): these bits selects whether interrupts irq 4 to irq 0 are requested by level sensing of pins irq 4 to irq 0 , or by falling-edge sensing. bits 4 to 0 irq4sc to irq0sc description 0 interrupts are requested when irq 4 to irq 0 inputs are low (initial value) 1 interrupts are requested by falling-edge input at irq 4 to irq 0 bit initial value read/write 7 ? 0 r/w these bits select level sensing or falling-edge sensing for irq 4 to irq 0 interrupts 6 ? 0 r/w 5 ? 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc 0 r/w irq to irq sense control 40 reserved bit 87 5.3 interrupt sources the interrupt sources include external interrupts (nmi, irq 0 to irq 4 ) and 21 internal interrupts. 5.3.1 external interrupts there are six external interrupts: nmi, and irq 0 to irq 4 . of these, nmi, irq 0 , irq 1 , and irq 2 can be used to exit software standby mode. nmi: nmi is the highest-priority interrupt and is always accepted, regardless of the states of the i and ui bits in ccr. the nmieg bit in syscr selects whether an interrupt is requested by the rising or falling edge of the input at the nmi pin. nmi interrupt exception handling has vector number 7. irq 0 to irq 4 interrupts: these interrupts are requested by input signals at pins irq 0 to irq 4 . the irq 0 to irq 4 interrupts have the following features. iscr settings can select whether an interrupt is requested by the low level of the input at pins irq 0 to irq 4 , or by the falling edge. ier settings can enable or disable the irq 0 to irq 4 interrupts. interrupt priority levels can be assigned by four bits in ipra (ipra7 to ipra4). the status of irq 0 to irq 4 interrupt requests is indicated in isr. the isr flags can be cleared to 0 by software. figure 5-2 shows a block diagram of interrupts irq 0 to irq 4 . figure 5-2 block diagram of interrupts irq 0 to irq 4 input edge/level sense circuit irqnsc irqnf s r q irqne irqn interrupt request clear signal irqn note: n = 4 to 0 88 figure 5-3 shows the timing of the setting of the interrupt flags (irqnf). figure 5-3 timing of setting of irqnf interrupts irq 0 to irq 4 have vector numbers 12 to 16. these interrupts are detected regardless of whether the corresponding pin is set for input or output. when using a pin for external interrupt input, clear its ddr bit to 0 and do not use the pin for chip select output, refresh output, or sci input or output. 5.3.2 internal interrupts twenty-one internal interrupts are requested from the on-chip supporting modules. each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. interrupt priority levels can be assigned in ipra and iprb. 5.3.3 interrupt vector table table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. in the default priority order, smaller vector numbers have higher priority. the priority of interrupts other than nmi can be changed in ipra and iprb. the priority order after a reset is the default order shown in table 5-3. irqn irqnf input pin 89 table 5-3 interrupt sources, vector addresses, and priority vector address * vector interrupt source origin number advanced mode normal mode ipr priority nmi external pins 7 h'001c to h'001f h'000e to h'000f high irq 0 12 h'0030 to h'0033 h'0018 to h'0019 ipra7 irq 1 13 h'0034 to h0037 h'001a to h'001b ipra6 irq 2 14 h'0038 to h'003b h'001c to h'001d ipra5 irq 3 15 h'003c to h'003f h'001e to h'001f irq 4 16 h'0040 to h'0043 h'0020 to h'0021 ipra4 reserved 17 h'0044 to h'0047 h'0022 to h'0023 18 h'0048 to h'004b h'0024 to h'0025 19 h'004c to h'004f h'0026 to h'0027 wovi (interval timer) watchdog timer 20 h'0050 to h'0053 h'0028 to h'0029 ipra3 reserved 21 h'0054 to h'0057 h'002a to h'002b 22 h'0058 to h'005b h'002c to h'002d 23 h'005c to h'005f h'002e to h'002f imia0 (compare match/ itu channel 0 24 h'0060 to h'0063 h'0030 to h'0031 ipra2 input capture a0) imib0 (compare match/ 25 h'0064 to h'0067 h'0032 to h'0033 input capture b0) ovi0 (overflow 0) 26 h'0068 to h'006b h'0034 to h'0035 reserved 27 h'006c to h'006f h'0036 to h'0037 imia1 (compare match/ itu channel 1 28 h'0070 to h'0073 h'0038 to h'0039 ipra1 input capture a1) imib1 (compare match/ 29 h'0074 to h'0077 h'003a to h'003b input capture b1) ovi1 (overflow 1) 30 h'0078 to h'007b h'003c to h'003d reserved 31 h'007c to h'007f h'003e to h'003f imia2 (compare match/ itu channel 2 32 h'0080 to h'0083 h'0040 to h'0041 ipra0 input capture a2) imib2 (compare match/ 33 h'0084 to h'0087 h'0042 to h'0043 input capture b2) ovi2 (overflow 2) 34 h'0088 to h'008b h'0044 to h'0045 reserved 35 h'008c to h'008f h'0046 to h'0047 note: * lower 16 bits of the address. 90 table 5-3 interrupt sources, vector addresses, and priority (cont) vector address * vector interrupt source origin number advanced mode normal mode ipr priority imia3 (compare match/ itu channel 3 36 h'0090 to h'0093 h'0048 to h'0049 iprb7 input capture a3) imib3 (compare match/ 37 h'0094 to h'0097 h'004a to h'004b input capture b3) ovi3 (overflow 3) 38 h'0098 to h'009b h'004c to h'004d reserved 39 h'009c to h'009f h'004e to h'004f imia4 (compare match/ itu channel 4 40 h'00a0 to h'00a3 h'0050 to h'0051 iprb6 input capture a4) imib4 (compare match/ 41 h'00a4 to h'00a7 h'0052 to h'0053 input capture b4) ovi4 (overflow 4) 42 h'00a8 to h'00ab h'0054 to h'0055 reserved 43 h'00ac to h'00af h'0056 to h'0057 reserved 44 h'00b0 to h'00b3 h'0058 to h'0059 45 h'00b4 to h'00b7 h'005a to h'005b 46 h'00b8 to h'00bb h'005c to h'005d 47 h'00bc to h'00bf h'005e to h'005f 48 h'00c0 to h'00c3 h'0060 to h'0061 49 h'00c4 to h'00c7 h'0062 to h'0063 50 h'00c8 to h'00cb h'0064 to h'0065 51 h'00cc to h'00cf h'0066 to h'0067 eri0 (receive error) sci 52 h'00d0 to h'00d3 h'0068 to h'0069 iprb3 rxi0 (receive data 53 h'00d4 to h'00d7 h'006a to h'006b full) txi0 (transmit data 54 h'00d8 to h'00db h'006c to h'006d empty) tei0 (transmit end) 55 h'00dc to h'00df h'006e to h'006f reserved 56 h'00e0 to h'00e3 h'0070 to h'0071 iprb2 57 h'00e4 to h'00e7 h'0072 to h'0073 58 h'00e8 to h'00eb h'0074 to h'0075 59 h'00ec to h'00ef h'0076 to h'0077 adi (a/d end) a/d 60 h'00f0 to h'00f3 h'0078 to h'0079 iprb1 low note: * lower 16 bits of the address. 91 5.4 interrupt operation 5.4.1 interrupt handling process the h8/3032 series handles interrupts differently depending on the setting of the ue bit. when ue = 1, interrupts are controlled by the i bit. when ue = 0, interrupts are controlled by the i and ui bits. table 5-4 indicates how interrupts are handled for all setting combinations of the ue, i, and ui bits. nmi interrupts are always accepted except in the reset and hardware standby states. irq interrupts and interrupts from the on-chip supporting modules have their own enable bits. interrupt requests are ignored when the enable bits are cleared to 0. table 5-4 ue, i, and ui bit settings and interrupt handling syscr ccr ue i ui description 1 0 all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 no interrupts are accepted except nmi. 0 0 all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 0 nmi and interrupts with priority level 1 are accepted. 1 no interrupts are accepted except nmi. ue = 1: interrupts irq 0 to irq 4 and interrupts from the on-chip supporting modules can all be masked by the i bit in the cpu s ccr. interrupts are masked when the i bit is set to 1, and unmasked when the i bit is cleared to 0. interrupts with priority level 1 have higher priority. figure 5-4 is a flowchart showing how interrupts are accepted when ue = 1. 92 figure 5-4 process up to interrupt acceptance when ue = 1 program execution state interrupt requested? nmi no yes no yes no priority level 1? no irq 0 yes no irq 1 yes adi yes no irq 0 yes no irq 1 yes adi yes no i = 0 yes save pc and ccr i 1 branch to interrupt service routine ? pending yes read vector address 93 if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. when the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted. if the i bit is set to 1, only nmi is accepted; other interrupt requests are held pending. when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. next the i bit is set to 1 in ccr, masking all interrupts except nmi. the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. ue = 0: the i and ui bits in the cpu s ccr and the ipr bits enable three-level masking of irq 0 to irq 4 interrupts and interrupts from the on-chip supporting modules. interrupt requests with priority level 0 are masked when the i bit is set to 1, and are unmasked when the i bit is cleared to 0. interrupt requests with priority level 1 are masked when the i and ui bits are both set to 1, and are unmasked when either the i bit or the ui bit is cleared to 0. for example, if the interrupt enable bits of all interrupt requests are set to 1, ipra is set to h'20, and iprb is set to h'00 (giving irq 2 and irq 3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. if i = 0, all interrupts are unmasked (priority order: nmi > irq 2 > irq 3 >irq 0 ?. b. if i = 1 and ui = 0, only nmi, irq 2 , and irq 3 are unmasked. c. if i = 1 and ui = 1, all interrupts are masked except nmi. 94 figure 5-5 shows the transitions among the above states. figure 5-5 interrupt masking state transitions (example) figure 5-6 is a flowchart showing how interrupts are accepted when ue = 0. if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. when the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted regardless of its ipr setting, and regardless of the ui bit. if the i bit is set to 1 and the ui bit is cleared to 0, only nmi and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. if the i bit and ui bit are both set to 1, only nmi is accepted; all other interrupt requests are held pending. when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. the i and ui bits are set to 1 in ccr, masking all interrupts except nmi. the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. all interrupts are unmasked only nmi, irq , and irq are unmasked exception handling, or i 1, ui 1 ?? a. b. 2 3 all interrupts are masked except nmi c. ui 0 ? i 0 ? exception handling, or ui 1 ? i 0 ? i 1, ui 0 ?? 95 figure 5-6 process up to interrupt acceptance when ue = 0 program execution state interrupt requested? nmi no yes no yes no priority level 1? no irq 0 yes no irq 1 yes adi yes no irq 0 yes no irq 1 yes adi yes no i = 0 yes no i = 0 yes ui = 0 yes no save pc and ccr i 1, ui 1 ? pending branch to interrupt service routine yes ? read vector address 96 5.4.2 interrupt sequence figure 5-7 shows the interrupt sequence in mode 1 when the program code and stack are in an on-chip memory area. figure 5-7 interrupt sequence (mode 2, stack in external memory) a to a interrupt request signal internal read signal internal write signal on-chip data 19 0 (1) (2), (4) (3) (5) (7) note: mode 1, with program code and stack in on-chip memory area. interrupt level decision and wait for end of instruction interrupt accepted instruction prefetch internal processing stack vector fetch internal processing prefetch of interrupt service routine instruction high instruction prefetch address (not executed; return address, same as pc contents) instruction code (not executed) instruction prefetch address (not executed) sp ?2 sp ?4 (6), (8) (9), (11) (10), (12) (13) (14) pc and ccr saved to stack vector address starting address of interrupt service routine (contents of vector address) starting address of interrupt service routine; (13) = (10), (12) first instruction of interrupt service routine (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 97 5.4.3 interrupt response time table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. table 5-5 interrupt response time external memory on-chip 8-bit bus no. item memory 2 states 3 states 1 interrupt priority decision 2 * 1 2 * 1 2 * 1 2 maximum number of states 1 to 23 1 to 27 1 to 31 * 4 until end of current instruction 3 saving pc and ccr to stack 4 8 12 * 4 4 vector fetch 4 8 12 * 4 5 instruction prefetch * 2 4812 * 4 6 internal processing * 3 444 total 19 to 41 31 to 57 43 to 73 notes: 1. 1 state for internal interrupts. 2. prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. internal processing after the interrupt is accepted and internal processing after prefetch. 4. the number of states increases if wait states are inserted in external memory access. 98 5.5 usage notes 5.5.1 contention between interrupt and interrupt-disabling instruction when an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. if an interrupt occurs while a bclr, mov, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. if a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. this also applies to the clearing of an interrupt flag. figure 5-8 shows an example in which an imiea bit is cleared to 0 in the itu. figure 5-8 contention between interrupt and interrupt-disabling instruction this type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. imia exception handling tier write cycle by cpu tier address internal address bus internal write signal imiea imia imfa interrupt signal 99 5.5.2 instructions that inhibit interrupts the ldc, andc, orc, and xorc instructions inhibit interrupts. when an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a cpu interrupt. if the cpu is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the cpu always continues by executing the next instruction. 5.5.3 interrupts during eepmov instruction execution the eepmov.b and eepmov.w instructions differ in their reaction to interrupt requests. when the eepmov.b instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even nmi. when the eepmov.w instruction is executing a transfer, interrupt requests other than nmi are not accepted until the transfer is completed. if nmi is requested, nmi exception handling starts at a transfer cycle boundary. the pc value saved on the stack is the address of the next instruction. programs should be coded as follows to allow for nmi interrupts during eepmov.w execution: l1: eepmov.w mov.w r4,r4 bne l1 100 section 6 bus controller 6.1 overview the h8/3032 series has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. this enables different types of memory to be connected easily. a bus arbitration function of the bus controller controls the operation of the dma controller (dmac) and refresh controller. the bus controller can also release the bus to an external device. 6.1.1 features features of the bus controller are listed below. independent settings for address areas 0 to 7 128-kbyte areas in 1-mbyte mode. areas can be designated for two-state or three-state access. four wait modes programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected. zero to three wait states can be inserted automatically. 101 6.1.2 block diagram figure 6-1 shows a block diagram of the bus controller. figure 6-1 block diagram of bus controller bus control circuit astcr wcer internal data bus access state control signal wait request signal internal signals wait-state controller wcr area decoder internal address bus wait legend astcr: wcer: wcr: access state control register wait state controller enable register wait control register 102 6.1.3 input/output pins table 6-1 summarizes the bus controller s input/output pins. table 6-1 bus controller pins name abbreviation i/o function address strobe as output strobe signal indicating valid address output on the address bus read rd output strobe signal indicating reading from the external address space write wr output strobe signal indicating writing to the external address space, with valid data on the data bus wait wait input wait request signal for access to external three- state-access areas 6.1.4 register configuration table 6-2 summarizes the bus controller s registers. table 6-2 bus controller registers address * name abbreviation r/w initial value h'ffed access state control register astcr r/w h'ff h'ffee wait control register wcr r/w h'f3 h'ffef wait state controller enable register wcer r/w h'ff note: * lower 16 bits of the address. 103 6.2 register descriptions 6.2.1 access state control register (astcr) astcr is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. astcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?rea 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is accessed in two or three states. bits 7 to 0 ast7 to ast0 description 0 areas 7 to 0 are accessed in two states 1 areas 7 to 0 are accessed in three states (initial value) astcr specifies the number of states in which external areas are accessed. on-chip memory and registers are accessed in a fixed number of states that does not depend on astcr settings. bit initial value read/write 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bits selecting number of states for access to each area 104 6.2.2 wait control register (wcr) wcr is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (wsc) and specifies the number of wait states. wcr is initialized to h'f3 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?eserved: read-only bits, always read as 1. bits 3 and 2?ait mode select 1 and 0 (wms1/0): these bits select the wait mode. bit 3 bit 2 wms1 wms0 description 0 0 programmable wait mode (initial value) 1 no wait states inserted by wait-state controller 1 0 pin wait mode 1 1 pin auto-wait mode bit initial value read/write 7 1 6 1 5 1 4 1 3 wms1 0 r/w 0 wc0 1 r/w 2 wms2 0 r/w 1 wc1 1 r/w wait count 1/0 these bits select the number of wait states inserted reserved bits wait mode select 1/0 these bits select the wait mode 105 bits 1 and 0?ait count 1 and 0 (wc1/0): these bits select the number of wait states inserted in access to external three-state-access areas. bit 1 bit 0 wc1 wc0 description 0 0 no wait states inserted by wait-state controller 1 1 state inserted 1 0 2 states inserted 1 3 states inserted (initial value) 6.2.3 wait state controller enable register (wcer) wcer is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. wcer is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ait-state controller enable 7 to 0 (wce7 to wce0): these bits enable or disable wait-state control of external three-state-access areas. bits 7 to 0 wce7 to wce0 description 0 wait-state control disabled (pin wait mode 0) 1 wait-state control enabled (initial value) bit initial value read/write 7 wce7 1 r/w 6 wce6 1 r/w 5 wce5 1 r/w 4 wce4 1 r/w 3 wce3 1 r/w 0 wce0 1 r/w 2 wce2 1 r/w 1 wce1 1 r/w wait state controller enable 7 to 0 these bits enable or disable wait-state control 106 6.3 operation 6.3.1 area division the external address space is divided into areas 0 to 7. each area has a size of 128 kbytes in the 1-mbyte mode. figure 6-2 shows a general view of the memory map. figure 6-2 access area map h'00000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 1 (128 kbytes) area 2 (128 kbytes) area 3 (128 kbytes) area 4 (128 kbytes) area 5 (128 kbytes) area 6 (128 kbytes) area 7 (128 kbytes) on-chip ram * 1, * 2 external address space * 3 on-chip i/o registers * 1 1-mbyte mode (mode 1) h'fffff area 0 (128 kbytes) on-chip rom * 1 notes: there is no area division in modes 2 and 3. 1. the number of access states to on-chip rom, on-chip ram, and on-chip i/o registers is fixed. 2. this area follows area 7 specifications when the rame bit in syscr is 0. 3. this area follows area 7 specifications. 107 the bus specifications for each area can be selected in astcr, wcer, and wcr as shown in table 6-3. table 6-3 bus specifications astcr wcer wcr bus specifications bus access astn wcen wms1 wms0 width states wait mode 0 8 2 disabled 1 0 8 3 pin wait mode 0 10083 programmable wait mode 1 8 3 disabled 1083 pin wait mode 1 1 8 3 pin auto-wait mode note: n = 0 to 7 108 6.3.2 bus control signal timing 8-bit, three-state-access areas: figure 6-3 shows the timing of bus control signals for an 8-bit, three-state-access area. wait states can be inserted. figure 6-3 bus control signal timing for 8-bit, three-state-access area bus cycle address bus as rd d 7 to d 0 wr d 7 to d 0 read access write access external address valid valid t 1 t 2 t 3 109 8-bit, two-state-access areas: figure 6-4 shows the timing of bus control signals for an 8-bit, two-state-access area. wait status cannot be inserted. figure 6-4 bus control signal timing for 8-bit, two-state-access area bus cycle address bus as rd d 7 to d 0 wr d 7 to d 0 read access valid valid write access t 1 t 2 external address 110 6.3.3 wait modes four wait modes can be selected for each area as shown in table 6-4. table 6-4 wait mode selection astcr wcer wcr astn bit wcen bit wms1 bit wms0 bit wsc control wait mode 0 disabled no wait states 1 0 disabled pin wait mode 0 1 0 0 enabled programmable wait mode 1 enabled no wait states 1 0 enabled pin wait mode 1 1 enabled pin auto-wait mode note: n = 7 to 0 the astn and wcen bits can be set independently for each area. bits wms1 and wms0 apply to all areas. all areas for which wsc control is enabled operate in the same wait mode. 111 pin wait mode 0: the wait state controller is disabled. wait states can only be inserted by wait pin control. during access to an external three-state-access area, if the wait pin is low at the fall of the system clock (? in the t 2 state, a wait state (t w ) is inserted. if the wait pin remains low, wait states continue to be inserted until the wait signal goes high. figure 6-5 shows the timing. figure 6-5 pin wait mode 0 ? pin address bus data bus as rd wr data bus t 1 t 2 t w t w t 3 inserted by signal write data ** * read data read access write access external address wait wait note: arrows indicate time of sampling of the pin. * wait 112 pin wait mode 1: in all accesses to external three-state-access areas, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. if the wait pin is low at the fall of the system clock (? in the last of these wait states, an additional wait state is inserted. if the wait pin remains low, wait states continue to be inserted until the wait signal goes high. pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. if the wait count is 0, this mode operates in the same way as pin wait mode 0. figure 6-6 shows the timing when the wait count is 1 (wc1 = 0, wc0 = 1) and one additional wait state is inserted by wait input. figure 6-6 pin wait mode 1 address bus data bus as rd wr t 1 t 2 t w t w t 3 write data * read data * read access write access note: arrows indicate time of sampling of the pin. * wait ? pin wait data bus external address write data inserted by wait count inserted by signal wait 113 pin auto-wait mode: if the wait pin is low, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. in pin auto-wait mode, if the wait pin is low at the fall of the system clock (? in the t 2 state, the number of wait states (t w ) selected by bits wc1 and wc0 are inserted. no additional wait states are inserted even if the wait pin remains low. figure 6-7 shows the timing when the wait count is 1. figure 6-7 pin auto-wait mode address bus data bus as rd wr data bus t 1 t 2 t 3 t 1 t 2 t w t 3 * * read data read data write data write data read access write access note: arrows indicate time of sampling of the pin. * wait external address external address wait 114 programmable wait mode: the number of wait states (t w ) selected by bits wc1 and wc0 are inserted in all accesses to external three-state-access areas. figure 6-8 shows the timing when the wait count is 1 (wc1 = 0, wc0 = 1). figure 6-8 programmable wait mode t 1 t 2 t w t 3 ? address bus as rd wr data bus data bus external address read data write data read access write access 115 example of wait state control settings: a reset initializes astcr and wcer to h'ff and wcr to h'f3, selecting programmable wait mode and three wait states for all areas. software can select other wait modes for individual areas by modifying the astcr, wcer, and wcr settings. figure 6-9 shows an example of wait mode settings. figure 6-9 wait mode settings (example) 76543210 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 bit: astcr h'0f: wcer h'33: wcr h'f3: area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 3-state-access area, programmable wait mode 3-state-access area, programmable wait mode 3-state-access area, pin wait mode 0 3-state-access area, pin wait mode 0 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted note: wait states cannot be inserted in areas designated for two-state access by astcr. 116 6.3.4 interconnections with memory (example) for each area, the bus controller can select two- or three-state access. in three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices. figure 6-10 shows an example of interconnections between the h8/3032 series and memory. figure 6-10 shows a memory map for this example. a 32-kword 8-bit eprom is connected to area 0. this device is accessed in three states via a 8- bit bus. two 32-kword 8-bit sram devices (sram1 and sram2) are connected to area 1. these devices are accessed in two states via a 8-bit bus. one 32-kword 8-bit sram (sram3) is connected to area 7. this device is accessed via an 8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode. figure 6-10 memory map (example) area 0 8-bit, three-state-access area area 1 8-bit, two-state-access area area 7 8-bit, three-state-access area (one auto-wait state) on-chip rom eprom not used sram1, 2 not used sram3 not used on-chip ram on-chip i/o registers h'00000 h'0ffff h'10000 h'17fff h'18000 h'1ffff h'20000 h'2ffff h'30000 h'3ffff h'e0000 h'e7fff h'fffff the bus width and the number of access states of the on-chip memories and registers are fixed; they cannot be changed by register setting. note: 117 6.4 usage notes 6.4.1 register write timing astcr and wcer write timing: data written to astcr or wcer takes effect starting from the next bus cycle. figure 6-11 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. figure 6-11 astcr write timing address t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 astcr address 3-state access to area 0 2-state access to area 0 118 119 section 7 i/o ports 7.1 overview the h8/3032 series has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, a, and b) and one input port (port 7). table 7-1 summarizes the port functions. the pins in each port are multiplexed as shown in table 7-1. each port has a data direction register (ddr) for selecting input or output, and a data register (dr) for storing output data. in addition to these registers, ports 2, and 5 have an input pull-up control register (pcr) for switching input pull-up transistors on and off. ports 1 to 3 and ports 5, 6, and 8 can drive one ttl load and a 90-pf capacitive load. ports 9, a, and b can drive one ttl load and a 30-pf capacitive load. ports 1 to 3 and ports 5, 6, 8, 9, a, and b can drive a darlington pair. ports 1, 2, 5, and b can drive leds (with 10-ma current sink). pins p8 2 to p8 0 , pa 7 to pa 0 , and pb 3 to pb 0 have schmitt-trigger input circuits. for block diagrams of the ports see appendix c, i/o port block diagrams. 120 table 7-1 port functions (1) port description pins mode 1 mode 2 mode 3 port 1 8-bit i/o port p1 7 to p1 0 / address output (a 7 to generic input/output can drive leds a 7 to a 0 a 0 ) and generic input ddr = 0: generic input ddr = 1: address output port 2 8-bit i/o port p2 7 to p2 0 / address output (a 15 to generic input/output input pull-up a 15 to a 8 a 8 ) and generic input can drive leds ddr = 0: generic input ddr = 1: address output port 3 8-bit i/o port p3 7 to p3 0 / data input/output (d 15 generic input/output d 7 to d 0 to d 8 ) port 5 4-bit i/o port p5 3 to p5 0 / address output (a 19 to generic input/output input pull-up a 19 to a 16 a 16 ) and generic input can drive leds ddr = 0: generic input ddr = 1: address output port 6 4-bit i/o port p6 5 / wr , bus control signal generic input/output p6 4 / rd , output ( wr , rd , as ) p6 3 / as p6 0 / wait bus control signal output ( wait ) and 1-bit generic input/ output port 7 ? 8-bit input port p7 7 to p7 0 / analog input (an 7 to an 0 ) to a/d converter, and generic input an 7 to an 0 port 8 ? 4-bit i/o port p8 3 /irq 3 , irq 3 to irq 0 input and 4-bit generic input/output ?p8 2 to p8 0 have p8 2 /irq 2 , schmitt inputs p8 1 /irq 1 p8 0 /irq 0 port 9 ? 3-bit i/o port p9 4 /sck/irq 4 input and output (sck) for serial communication interface (sci), irq 4 input, and 1-bit generic input/output p9 2 /rxd, input and output (rxd and txd) for sci and 2-bit generic p9 0 /txd input/output 121 table 7-1 port functions (1) port description pins mode 1 mode 2 mode 3 port a 8-bit i/o port pa 7 /tp 7 /tiocb 2 /, tpc output (tp 8 to tp 0 ), itu input and output (tclkd, schmitt inputs pa 6 /tp 6 /tioca 2 , tclkc, tclkb, tclka, tiocb 2 , tioca 2 , tiocb 1 , tioca 1 ), pa 5 /tp 5 /tiocb 1 , and generic input/output pa 4 /tp 4 //tioca 1 , pa 3 /tp 3 /tiocb 0 / tclkd, pa 2 /tp 2 /tioca 0 / tclkc, pa 1 /tp 1 /tclkb, pa 0 /tp 0 /tclka port b 8-bit i/o port pb 7 /tp 15 / adtrg , tpc output (tp 15 ), trigger input ( adtrg ) to a/d converter, ? can drive leds and 1-bit generic input/output ?pb 3 to pb 0 pb 6 /tp 14 tpc output (tp 14 ) and 1-bit generic input/output have schmitt pb 5 /tp 13 /tocxb 4 , tpc output (tp 13 to tp 8 ), itu input and output (tocxb 4 , inputs pb 4 /tp 12 /tocxa 4 , tocxa 4 , tiocb 4 , tioca 4 , tiocb 3 , tioca 3 ), and tocxa 4 , pb 3 /tp 11 /tiocb 4 , tiocb 4 , tioca 4 , tiocb 3 , tioca 3 ), and 6-bit generic pb 2 /tp 10 /tioca 4 , input/output pb 1 /tp 9 /tiocb 3 , pb 0 /tp 8 /tioca 3 122 7.2 port 1 7.2.1 overview port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. the pin functions differ depending on the operating mode. in mode 1, they are address bus output pins (a 7 to a 0 ). in modes 2 and 3, port 1 is a generic input/output port. pins in port 1 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 7-1 port 1 pin configuration port 1 p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) 7 6 5 4 3 2 1 0 port 1 pins modes 2 and 3 modes 1 p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 123 7.2.2 register descriptions table 7-2 summarizes the registers of port 1. table 7-2 port 1 registers address * name abbreviation r/w initial value h'ffc0 port 1 data direction register p1ddr w h'00 h'ffc2 port 1 data register p1dr r/w h'00 note: * lower 16 bits of the address. port 1 data direction register (p1ddr): p1ddr is an 8-bit write-only register that can select input or output for each pin in port 1. mode 1: a pin in port 1 becomes an address output pin if the corresponding p1ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. modes 2 and 3 (single-chip modes): port 1 functions as an input/output port. a pin in port 1 becomes an output pin if the corresponding p1ddr bit is set to 1, and an input pin if this bit is cleared to 0. p1ddr is a write-only register. its value cannot be read. all bits return 1 when read. p1ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p1ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. bit initial value read/write 7 p1 ddr 0 w 7 6 p1 ddr 0 w 6 5 p1 ddr 0 w 5 4 p1 ddr 0 w 4 3 p1 ddr 0 w 3 2 p1 ddr 0 w 2 1 p1 ddr 0 w 1 0 p1 ddr 0 w 0 port 1 data direction 7 to 0 these bits select input or output for port 1 pins 124 port 1 data register (p1dr): p1dr is an 8-bit readable/writable register that stores data for pins p1 7 to p1 0 . when a bit in p1ddr is set to 1, if port 1 is read the value of the corresponding p1dr bit is returned directly, regardless of the actual state of the pin. when a bit in p1ddr is cleared to 0, if port 1 is read the corresponding pin level is read. p1dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7.2.3 pin functions in each mode the pin functions of port 1 differ between mode 1 and modes 2 and 3 (single-chip modes). the pin functions in each mode are described below. bit initial value read/write 7 p1 0 r/w port 1 data 7 to 0 these bits store data for port 1 pins 7 6 p1 0 r/w 6 5 p1 0 r/w 5 4 p1 0 r/w 4 3 p1 0 r/w 3 2 p1 0 r/w 2 1 p1 0 r/w 1 0 p1 0 r/w 0 125 mode 1: address output or generic input can be selected for each pin in port 1. a pin becomes an address output pin if the corresponding p1ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. following a reset, all pins are input pins. to use a pin for address output, its p1ddr bit must be set to 1. figure 7-2 shows the pin functions in mode 1. figure 7-2 pin functions in mode 1 (port 1) modes 2 and 3 (single-chip modes): input or output can be selected separately for each pin in port 1. a pin becomes an output pin if the corresponding p1ddr bit is set to 1, and an input pin if this bit is cleared to 0. figure 7-3 shows the pin functions in modes 2 and 3. figure 7-3 pin functions in modes 2 and 3 (port 1) port 1 a (output) a (output) a (output) a (output) a (output) a (output) a (output) a (output) 7 6 5 4 3 2 1 0 when p1ddr = 1 p1 (input) p1 (input) p1 (input) p1 (input) p1 (input) p1 (input) p1 (input) p1 (input) 7 6 5 4 3 2 1 0 when p1ddr = 0 port 1 p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) 7 6 5 4 3 2 1 0 126 7.3 port 2 7.3.1 overview port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-4. the pin functions differ depending on the operating mode. in mode 1, settings in the port 1 data direction register (p1ddr) can designate pins for address bus output (a 15 to a 8 ) or generic input. in modes 2 and 3, port 2 is a generic input/output port. port 2 has software-programmable built-in pull-up transistors. pins in port 2 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 7-4 port 2 pin configuration port 2 p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) 7 6 5 4 3 2 1 0 port 2 pins modes 2 and 3 p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) 7 6 5 4 3 2 1 0 mode 1 15 14 13 12 11 10 9 8 127 7.3.2 register descriptions table 7-3 summarizes the registers of port 2. table 7-3 port 2 registers address * name abbreviation r/w initial value h'ffc1 port 2 data direction register p2ddr w h'00 h'ffc3 port 2 data register p2dr r/w h'00 h'ffd8 port 2 input pull-up control register p2pcr r/w h'00 note: * lower 16 bits of the address. port 2 data direction register (p2ddr): p2ddr is an 8-bit write-only register that can select input or output for each pin in port 2. mode 1: a pin in port 2 becomes an address output pin if the corresponding p2ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. modes 2 and 3: port 2 functions as an input/output port. a pin in port 2 becomes an output pin if the corresponding p2ddr bit is set to 1, and an input pin if this bit is cleared to 0. p2ddr is a write-only register. its value cannot be read. all bits return 1 when read. p2ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p2ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. bit initial value read/write 7 p2 ddr 0 w 7 6 p2 ddr 0 w 6 5 p2 ddr 0 w 5 4 p2 ddr 0 w 4 3 p2 ddr 0 w 3 2 p2 ddr 0 w 2 1 p2 ddr 0 w 1 0 p2 ddr 0 w 0 port 2 data direction 7 to 0 these bits select input or output for port 2 pins 128 port 2 data register (p2dr): p2dr is an 8-bit readable/writable register that stores data for pins p2 7 to p2 0 . when a bit in p2ddr is set to 1, if port 2 is read the value of the corresponding p2dr bit is returned directly, regardless of the actual state of the pin. when a bit in p2ddr is cleared to 0, if port 2 is read the corresponding pin level is read. p2dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 2 input pull-up control register (p2pcr): p2pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 2. when a p2ddr bit is cleared to 0 (selecting generic input), if the corresponding bit from p2 7 pcr to p2 0 pcr is set to 1, the input pull-up transistor is turned on. p2pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7.3.3 pin functions in each mode the pin functions of port 2 differ between mode 1 and modes 2 and 3. the pin functions in each mode are described below. bit initial value read/write 7 p2 0 r/w port 2 data 7 to 0 these bits store data for port 2 pins 7 6 p2 0 r/w 6 5 p2 0 r/w 5 4 p2 0 r/w 4 3 p2 0 r/w 3 2 p2 0 r/w 2 1 p2 0 r/w 1 0 p2 0 r/w 0 bit initial value read/write 7 p2 pcr 0 r/w port 2 input pull-up control 7 to 0 these bits control input pull-up transistors built into port 2 7 6 p2 pcr 0 r/w 6 5 p2 pcr 0 r/w 5 4 p2 pcr 0 r/w 4 3 p2 pcr 0 r/w 3 2 p2 pcr 0 r/w 2 1 p2 pcr 0 r/w 1 0 p2 pcr 0 r/w 0 129 mode 1: address output or generic input can be selected for each pin in port 2. a pin becomes an address output pin if the corresponding p2ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. following a reset, all pins are input pins. to use a pin for address output, its p2ddr bit must be set to 1. figure 7-5 shows the pin functions in mode 1. figure 7-5 pin functions in mode 1 (port 2) modes 2 and 3: input or output can be selected separately for each pin in port 2. a pin becomes an output pin if the corresponding p2ddr bit is set to 1, and an input pin if this bit is cleared to 0. figure 7-6 shows the pin functions in modes 2 and 3. figure 7-6 pin functions in modes 2 and 3 (port 2) port 2 a (output) a (output) a (output) a (output) a (output) a (output) a (output) a (output) 15 14 13 12 11 10 9 8 when p2ddr = 1 p2 (input) p2 (input) p2 (input) p2 (input) p2 (input) p2 (input) p2 (input) p2 (input) 7 6 5 4 3 2 1 0 when p2ddr = 0 port 2 p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) 7 6 5 4 3 2 1 0 130 7.3.4 input pull-up transistors port 2 has built-in mos input pull-up transistors that can be controlled by software. these input pull-up transistors can be turned on and off individually. when a p2pcr bit is set to 1 and the corresponding p2ddr bit is cleared to 0, the input pull-up transistor is turned on. the input pull-up transistors are turned off by a reset and in hardware standby mode. in software standby mode they retain their previous state. table 7-4 summarizes the states of the input pull-up transistors in each mode. table 7-4 input pull-up transistor states (port 2) mode reset hardware standby mode software standby mode other modes 1 off off on/off on/off 2 3 legend off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p2pcr = 1 and p2ddr = 0. otherwise, it is off. 131 7.4 port 3 7.4.1 overview port 3 is an 8-bit input/output port with the pin configuration shown in figure 7-7. port 3 is a data bus in mode 1 and a generic input/output port in modes 2 and 3. pins in port 3 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 7-7 port 3 pin configuration 7.4.2 register descriptions table 7-5 summarizes the registers of port 3. table 7-5 port 3 registers address * name abbreviation r/w initial value h'ffc4 port 3 data direction register p3ddr w h'00 h'ffc6 port 3 data register p3dr r/w h'00 note: * lower 16 bits of the address. port 3 p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) 7 6 5 4 3 2 1 0 d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) 7 6 5 4 3 2 1 0 port 3 pins modes 2 and 3 mode 1 132 port 3 data direction register (p3ddr): p3ddr is an 8-bit write-only register that can select input or output for each pin in port 3. mode 1: port 3 functions as a data bus. p3ddr is ignored. modes 2 and 3: port 3 functions as an input/output port. a pin in port 3 becomes an output pin if the corresponding p3ddr bit is set to 1, and an input pin if this bit is cleared to 0. p3ddr is a write-only register. its value cannot be read. all bits return 1 when read. p3ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p3ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port 3 data register (p3dr): p3dr is an 8-bit readable/writable register that stores data for pins p3 7 to p3 0 . when a bit in p3ddr is set to 1, if port 3 is read the value of the corresponding p3dr bit is returned directly, regardless of the actual state of the pin. when a bit in p3ddr is cleared to 0, if port 3 is read the corresponding pin level is read. p3dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. bit initial value read/write 7 p3 ddr 0 w port 3 data direction 7 to 0 these bits select input or output for port 3 pins 7 6 p3 ddr 0 w 6 5 p3 ddr 0 w 5 4 p3 ddr 0 w 4 3 p3 ddr 0 w 3 2 p3 ddr 0 w 2 1 p3 ddr 0 w 1 0 p3 ddr 0 w 0 bit initial value read/write 7 p3 0 r/w port 3 data 7 to 0 these bits store data for port 3 pins 7 6 p3 0 r/w 6 5 p3 0 r/w 5 4 p3 0 r/w 4 3 p3 0 r/w 3 2 p3 0 r/w 2 1 p3 0 r/w 1 0 p3 0 r/w 0 133 7.4.3 pin functions in each mode the pin functions of port 3 differ between modes 1 and modes 2 and 3. the pin functions in each mode are described below. mode 1: all pins of port 3 automatically become data input/output pins. figure 7-8 shows the pin functions in mode 1. figure 7-8 pin functions in mode 1 (port 3) modes 2 and 3: input or output can be selected separately for each pin in port 3. a pin becomes an output pin if the corresponding p3ddr bit is set to 1, and an input pin if this bit is cleared to 0. figure 7-9 shows the pin functions in modes 2 and 3. figure 7-9 pin functions in modes 2 and 3 (port 3) port 3 d 7 (input/output) d 6 (input/output) d 5 (input/output) d 4 (input/output) d 3 (input/output) d 2 (input/output) d 1 (input/output) d 0 (input/output) port 3 p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) 7 6 5 4 3 2 1 0 134 7.5 port 5 7.5.1 overview port 5 is a 4-bit input/output port with the pin configuration shown in figure 7-10. the pin functions differ depending on the operating mode. in mode 1, settings in the port 5 data direction register (p5ddr) designate pins for address bus output (a 19 to a 16 ) or generic input. in modes 2 and 3, port 5 is a generic input/output port. port 5 has software-programmable built-in pull-up transistors. pins in port 5 can drive one ttl load and a 90-pf capacitive load. they can also drive a led or a darlington transistor pair. figure 7-10 port 5 pin configuration 7.5.2 register descriptions table 7-6 summarizes the registers of port 5. table 7-6 port 5 registers address * name abbreviation r/w initial value h'ffc8 port 5 data direction register p5ddr w h'f0 h'ffca port 5 data register p5dr r/w h'f0 h'ffdb port 5 input pull-up control register p5pcr r/w h'f0 note: * lower 16 bits of the address. port 5 p5 /a p5 /a p5 /a p5 /a 3 2 1 0 19 18 17 16 p5 (input)/a (output) p5 (input)/a (output) p5 (input)/a (output) p5 (input)/a (output) 3 2 1 0 port 5 pins mode 1 p5 (input/output) p5 (input/output) p5 (input/output) p5 (input/output) 3 2 1 0 modes 2 and 3 19 18 17 16 135 port 5 data direction register (p5ddr): p5ddr is an 8-bit write-only register that can select input or output for each pin in port 5. mode 1: a pin in port 5 becomes an address output pin if the corresponding p5ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. modes 2 and 3: port 5 functions as an input/output port. a pin in port 5 becomes an output pin if the corresponding p5ddr bit is set to 1, and an input pin if this bit is cleared to 0. p5ddr is a write-only register. its value cannot be read. all bits return 1 when read. p5ddr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p5ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port 5 data register (p5dr): p5dr is an 8-bit readable/writable register that stores data for pins p5 3 to p5 0 . when a bit in p5ddr is set to 1, if port 5 is read the value of the corresponding p5dr bit is returned directly, regardless of the actual state of the pin. when a bit in p5ddr is cleared to 0, if port 5 is read the corresponding pin level is read. bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 p5 ddr 0 w 3 2 p5 ddr 0 w 2 1 p5 ddr 0 w 1 0 p5 ddr 0 w 0 reserved bits port 5 data direction 3 to 0 these bits select input or output for port 5 pins bit initial value read/write 7 1 6 1 5 1 4 1 3 p5 0 r/w 3 2 p5 0 r/w 2 1 p5 0 r/w 1 0 p5 0 r/w 0 reserved bits these bits store data for port 5 pins port 5 data 3 to 0 136 bits p5 7 to p5 4 are reserved. they can be written and read, but they cannot be used for port input or output. p5dr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 5 input pull-up control register (p5pcr): p5pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 5. when a p5ddr bit is cleared to 0 (selecting generic input), if the corresponding bit from p5 3 pcr to p5 0 pcr is set to 1, the input pull-up transistor is turned on. p5pcr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. bit initial value read/write 7 1 6 1 5 1 4 1 3 p5 pcr 0 r/w 3 2 p5 pcr 0 r/w 2 1 p5 pcr 0 r/w 1 0 p5 pcr 0 r/w 0 reserved bits these bits control input pull-up transistors built into port 5 port 5 input pull-up control 3 to 0 137 7.5.3 pin functions in each mode the functions of port 5 differ depending on the operating mode. the pin functions in each mode are described below. mode 1: address output or generic input can be selected for each pin in port 5. a pin becomes an address output pin if the corresponding p5ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. following a reset, all pins are input pins. to use a pin for address output, its p5ddr must be set to 1. figure 7-11 shows the pin functions in mode 1. figure 7-11 pin functions in mode 1 (port 5) modes 2 and 3: input or output can be selected separately for each pin in port 5. a pin becomes an output pin if the corresponding p5ddr bit is set to 1, and an input pin if this bit is cleared to 0. figure 7-12 shows the pin functions in modes 2 and 3. figure 7-12 pin functions in modes 2 and 3 (port 5) port 5 a (output) a (output) a (output) a (output) 19 18 17 16 when p5ddr = 1 p5 (input) p5 (input) p5 (input) p5 (input) 3 2 1 0 when p5ddr = 0 port 5 p5 (input/output) p5 (input/output) p5 (input/output) p5 (input/output) 3 2 1 0 138 7.5.4 input pull-up transistors port 5 has built-in mos pull-up transistors that can be controlled by software. these input pull-up transistors can be turned on and off individually. when a p5pcr bit is set to 1 and the corresponding p5ddr bit is cleared to 0, the input pull-up transistor is turned on. the input pull-up transistors are turned off by a reset and in hardware standby mode. in software standby mode they retain their previous state. table 7-7 summarizes the states of the input pull-up transistors in each mode. table 7-7 input pull-up transistor states (port 5) mode reset hardware standby mode software standby mode other modes 1 off off on/off on/off 2 3 legend off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p5pcr = 1 and p5ddr = 0. otherwise, it is off. 139 7.6 port 6 7.6.1 overview port 6 is a 4-bit input/output port that is also used for input and output of bus control signals ( wr , rd , as , and wait ). figure 7-13 shows the pin configuration of port 6. in mode 1, the pin functions are wr , rd , as , and p6 0 / wait . in modes 2 and 3, port 6 is a generic input/output port. pins in port 6 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 7-13 port 6 pin configuration 7.6.2 register descriptions table 7-8 summarizes the registers of port 6. table 7-8 port 6 registers address * name abbreviation r/w initial value h'ffc9 port 6 data direction register p6ddr w h'80 h'ffcb port 6 data register p6dr r/w h'80 note: * lower 16 bits of the address. port 6 p6 / p6 / p6 / p6 / 5 4 3 0 wr rd as wait port 6 pins wr rd as p6 modes 1 p6 p6 p6 p6 5 4 3 0 modes 2 and 3 (input/output) (input/output) (input/output) (input/output) (output) (output) (output) (input/output)/ wait (input) 140 port 6 data direction register (p6ddr): p6ddr is an 8-bit write-only register that can select input or output for each pin in port 6. mode 1: pins p6 5 to p6 3 function as bus control output pins ( wr , rd , as ). p6 0 functions as an input/output pin. when p6 0 ddr is set to 1, p6 0 is an output pin, and when p6 0 ddr is 0, p6 0 is an input pin. the p6 5 ddr to p6 3 ddr bit settings are ignored. modes 2 and 3: port 6 is a generic input/output port. a pin in port 6 becomes an output pin if the corresponding p6ddr bit is set to 1, and an input pin if this bit is cleared to 0. bits 7, 6, 2, and 1 are reserved. p6ddr is a write-only register. its value cannot be read. all bits return 1 when read. p6ddr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p6ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port 6 data register (p6dr): p6dr is an 8-bit readable/writable register that stores data for pins p6 5 to p6 3 and p6 0 . bit initial value read/write 7 ? 1 6 ? 0 w 5 p6 ddr 0 w 5 4 p6 ddr 0 w 4 3 p6 ddr 0 w 3 2 ? 0 w 1 ? 0 w 0 p6 ddr 0 w 0 port 6 data direction 6 to 0 these bits select input or output for port 6 pins reserved bit bit initial value read/write 7 ? 1 6 ? 0 r/w 5 p6 0 r/w 5 4 p6 0 r/w 4 3 p6 0 r/w 3 2 ? 0 r/w 1 ? 0 r/w 0 p6 0 r/w 0 reserved bit port 6 data 5 to 3, 0 these bits store data for port 6 pins 141 when a bit in p6ddr is set to 1, if port 6 is read the value of the corresponding p6dr bit is returned directly. when a bit in p6ddr is cleared to 0, if port 6 is read the corresponding pin level is read. bits 7, 6, 2, and 1 are reserved. bit 7 cannot be modified and always reads 1. bits 6, 2, and 1 can be written and read, but cannot be used as ports. if bit 6, 2, or 1 in p6ddr is read while its value is 1, the value of the corresponding bit in p6dr will be read. if bit 6, 2, or 1 in p6ddr is read while its value is 0, if will always read 1. p6dr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7.6.3 pin functions in each mode mode 1: p6 5 to p6 3 function as bus control output pins. p6 0 is either a bus control input pin or generic input/output pin, functioning as an output pin when bit p6 0 ddr is set to 1 and an input pin when this bit is cleared to 0. figure 7-14 and table 7-9 indicate the pin functions in mode 1. figure 7-14 pin functions in mode 1 (port 6) port 6 wr rd as p6 0 (input/output)/ wait (input) (output) (output) (output) 142 table 7-9 port 6 pin functions in mode 1 pin pin functions and selection method p6 5 / wr functions as follows regardless of p6 5 ddr p6 5 ddr 0 1 pin function wr output p6 4 / rd functions as follows regardless of p6 4 ddr p6 4 ddr 0 1 pin function rd output p6 3 / as functions as follows regardless of p6 3 ddr p6 3 ddr 0 1 pin function as output p6 0 / wait bits wce7 to wce0 in wcer, bit wms1 in wcr, and bit p6 0 ddr select the pin function as follows wcer all 1s not all 1s wms1 0 1 p6 0 ddr 0 1 0 * 0 * pin function p6 0 input p6 0 output wait input note: * do not set bit p6 0 ddr to 1. 143 modes 2 and 3: input or output can be selected separately for each pin in port 6. a pin becomes an output pin if the corresponding p6ddr bit is set to 1, and an input pin if this bit is cleared to 0. figure 7-15 shows the pin functions in modes 2 and 3. figure 7-15 pin functions in modes 2 and 3 (port 6) port 6 p6 p6 p6 p6 5 4 3 0 (input/output) (input/output) (input/output) (input/output) 144 7.7 port 7 7.7.1 overview port 7 is an 8-bit input port that is also used for analog input to the a/d converter. the pin functions are the same in all operating modes. figure 7-16 shows the pin configuration of port 7. figure 7-16 port 7 pin configuration port 7 p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 7 pins 145 7.7.2 register description table 7-10 summarizes the port 7 register. port 7 is an input-only port, so it has no data direction register. table 7-10 port 7 data register address * name abbreviation r/w initial value h'ffce port 7 data register p7dr r undetermined note: * lower 16 bits of the address. port 7 data register (p7dr) when port 7 is read, the pin levels are always read. bit initial value read/write 0 p7 ? r * note: * 0 1 p7 ? r * 1 2 p7 ? r * 2 3 p7 ? r * 3 4 p7 ? r * 4 5 p7 ? r * 5 6 p7 ? r * 6 7 p7 ? r * 7 70 determined by pins p7 to p7 . 146 7.8 port 8 7.8.1 overview port 8 is a 4-bit input/output port that is also used for irq 3 to irq 0 input. figure 7-17 shows the pin configuration of port 8. pin p8 0 functions as input/output pin or as an irq 0 input pin. pins p8 3 to p8 1 function as either input pins or irq 3 to irq 1 input pins in mode 1, and as input/output pins or irq 3 to irq 1 input pins in modes 2 and 3. pins in port 8 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. pins p8 2 to p8 0 have schmitt-trigger inputs. figure 7-17 port 8 pin configuration port 8 port 8 pins p8 3 (input)/irq 3 (input) p8 2 (input)/irq 2 (input) p8 1 (input)/irq 1 (input) p8 0 (input/output)/irq 0 (input) mode 1 p8 3 /irq 3 p8 2 /irq 2 p8 1 /irq 1 p8 0 /irq 0 p8 3 (input/output)/irq 3 (input) p8 2 (input/output)/irq 2 (input) p8 1 (input/output)/irq 1 (input) p8 0 (input/output)/irq 0 (input) modes 2 and 3 147 7.8.2 register descriptions table 7-11 summarizes the registers of port 8. table 7-11 port 8 registers address * name abbreviation r/w initial value h'ffcd port 8 data direction p8ddr w h'e0 register h'ffcf port 8 data register p8dr r/w h'e0 note: * lower 16 bits of the address. port 8 data direction register (p8ddr): p8ddr is an 8-bit write-only register that can select input or output for each pin in port 8. mode 1 pins p8 3 to p8 1 function as input pins. do not set p8 3 ddr to p8 1 ddr to 1. pin p8 0 functions as an output pin when p8 0 ddr is set to 1, and as input pin when p8 0 ddr is cleared to 0. modes 2 and 3 port 8 is a generic input/output port. a pin port 8 becomes an output pin if the corresponding p8ddr bit is set to 1, and an input pin if this bit is cleared to 0. bits 7 to 4 are reserved bits. p8ddr is a write-only register. its value cannot be read. all bits return 1 when read. p8ddr is initialized to h'e0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p8ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. 7 ? 1 6 ? 1 5 ? 1 4 ? 0 w 3 p8 ddr 0 w 3 2 p8 ddr 0 w 2 1 p8 ddr 0 w 1 0 p8 ddr 0 w 0 reserved bits port 8 data direction 3 to 0 these bits select input or output for port 8 pins bit initial value read/write 148 port 8 data register (p8dr): p8dr is an 8-bit readable/writable register that stores data for pins p8 3 to p8 0 . when a bit in p8ddr is set to 1, if port 8 is read the value of the corresponding p8dr bit is returned directly. when a bit in p8ddr is cleared to 0, if port 8 is read the corresponding pin level is read. bits 7 to 4 are reserved. bits 7 to 5 cannot be modified and always read 1. bit 4 can be written and read, but it cannot be used for port input or output. if bit 4 of p8ddr is read while its value is 1, bit 4 of p8dr is read directly. if bit 4 of p8ddr is read while its value is 0, it always reads 1. p8dr is initialized to h'e0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7.8.3 pin functions the port 8 pins are also used for irq 3 to irq 0 . table 7-12 describes the selection of pin functions. bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 0 r/w 3 p8 0 r/w 3 2 p8 0 r/w 2 1 p8 0 r/w 1 0 p8 0 r/w 0 reserved bits port 8 data 4 to 0 these bits store data for port 8 pins 149 table 7-12 port 8 pin functions pin pin functions and selection method p8 3 /irq 3 bit p8 3 ddr selects the pin function as follows p8 3 ddr 0 1 mode 1 modes 2 and 3 pin function p8 3 input illegal setting p8 3 output irq 3 input p8 2 /irq 2 bit p8 2 ddr selects the pin function as follows p8 2 ddr 0 1 mode 1 modes 2 and 3 pin function p8 2 input illegal setting p8 2 output irq 2 input p8 1 /irq 1 bit p8 1 ddr selects the pin function as follows p8 1 ddr 0 1 mode 1 modes 2 and 3 pin function p8 1 input illegal setting p8 1 output irq 1 input p8 0 /irq 0 bit p8 0 ddr selects the pin function as follows p8 0 ddr 0 1 pin function p8 0 input p8 0 output irq 0 input 150 7.9 port 9 7.9.1 overview port 9 is a 3-bit input/output port that is also used for input and output (txd, rxd, sck) by serial communication interface (sci), and for irq 4 input. port 9 has the same set of pin functions in all operating modes. figure 7-18 shows the pin configuration of port 9. pins in port 9 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. figure 7-18 port 9 pin configuration 7.9.2 register descriptions table 7-13 summarizes the registers of port 9. table 7-13 port 9 registers address * name abbreviation r/w initial value h'ffd0 port 9 data direction register p9ddr w h'c0 h'ffd2 port 9 data register p9dr r/w h'c0 note: * lower 16 bits of the address. port 9 p9 4 (input/output)/sck (input/output)/irq 4 (input) p9 2 (input/output)/rxd (input) p9 0 (input/output)/txd (output) port 9 pins 151 port 9 data direction register (p9ddr): p9ddr is an 8-bit write-only register that can select input or output for each pin in port 9. a pin in port 9 becomes an output pin if the corresponding p9ddr bit is set to 1, and an input pin if this bit is cleared to 0. p9ddr is a write-only register. its value cannot be read. all bits return 1 when read. p9ddr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a p9ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port 9 data register (p9dr): p9dr is an 8-bit readable/writable register that stores data for pins p9 4 , p9 2 , and p9 0 . when a bit in p9ddr is set to 1, if port 9 is read the value of the corresponding p9dr bit is returned directly. when a bit in p9ddr is cleared to 0, if port 9 is read the corresponding pin level is read. bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 w 4 p9 ddr 0 w 4 3 ? 0 w 2 p9 ddr 0 w 2 1 ? 0 w 0 p9 ddr 0 w 0 reserved bits port 9 data direction 4, 2, 0 these bits select input or output for port 9 pins bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 r/w 4 p9 0 r/w 4 3 ? 0 r/w 2 p9 0 r/w 2 1 ? 0 r/w 0 p9 0 r/w 0 reserved bits port 9 data 4, 2, 0 these bits store data for port 9 pins 152 bits 7 to 5, 3 and 1 are reserved. bits 7 and 6 cannot be modified and always read 1. bits 5, 3, and 1 can be written and read, but they cannot be used for port input or output. if bit 5, 3, or 1 in p9ddr is read while its value is 1, the corresponding bit in p9dr is read directly. if bit 5, 3, or 1 in p9ddr is read while its value is 0, it always reads 1. p9dr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 7.9.3 pin functions the port 9 pins are also used for sci input and output (txd, rxd, sck), and for irq 4 input. table 7-14 describes the selection of pin functions. table 7-14 port 9 pin functions pin pin functions and selection method p9 4 /sck/irq 4 bit c/ a in smr of sci, bits cke0 and cke1 in scr of sci, and bit p9 4 ddr select the pin function as follows cke1 0 1 c/ a 01 cke0 0 1 p9 4 ddr 0 1 pin function p9 4 p9 4 sck output sck output sck input input output irq 4 input p9 2 /rxd bit re in scr of sci and bit p9 2 ddr select the pin function as follows re 0 1 p9 2 ddr 0 1 pin function p9 2 input p9 2 output rxd input p9 0 /txd bit te in scr of sci and bit p9 0 ddr select the pin function as follows te 0 1 p9 0 ddr 0 1 pin function p9 0 input p9 0 output txd output 153 7.10 port a 7.10.1 overview port a is an 8-bit input/output port that is also used for output (tp 7 to tp 0 ) from the programmable timing pattern controller (tpc) and input and output (tiocb 2 , tioca 2 , tiocb 1 , tioca 1 , tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka) by the 16-bit integrated timer unit (itu), figure 7-19 shows the pin configuration of port a. pins in port a can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port a has schmitt-trigger inputs. figure 7-19 port a pin configuration port a pa /tp /tiocb pa /tp /tioca pa /tp /tiocb pa /tp /tioca pa /tp /tiocb /tclkd pa /tp /tioca /tclkc pa /tp /tend /tclkb pa /tp /tend /tclka 7 6 5 4 3 2 1 0 port a pins 7 6 5 4 3 2 1 0 2 2 1 1 1 0 0 0 154 7.10.2 register descriptions table 7-15 summarizes the registers of port a. table 7-15 port a registers address * name abbreviation r/w initial value h'ffd1 port a data direction register paddr w h'00 h'ffd3 port a data register padr r/w h'00 note: * lower 16 bits of the address. port a data direction register (paddr): paddr is an 8-bit write-only register that can select input or output for each pin in port a. a pin in port a becomes an output pin if the corresponding paddr bit is set to 1, and an input pin if this bit is cleared to 0. paddr is a write-only register. its value cannot be read. all bits return 1 when read. paddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a paddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. 7 pa ddr 0 w port a data direction 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 bit initial value read/write 155 port a data register (padr): padr is an 8-bit readable/writable register that stores data for pins pa 7 to pa 0 . when a bit in paddr is set to 1, if port a is read the value of the corresponding padr bit is returned directly. when a bit in paddr is cleared to 0, if port a is read the corresponding pin level is read. padr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. when port a pins are used for tpc output, padr stores output data for tpc output groups 0 and 1. if a bit in the next data enable register (ndera) is set to 1, the corresponding padr bit cannot be written. in this case, padr can be updated only when data is transferred from ndra. bit initial value read/write 0 pa 0 r/w 0 1 pa 0 r/w 1 2 pa 0 r/w 2 3 pa 0 r/w 3 4 pa 0 r/w 4 5 pa 0 r/w 5 6 pa 0 r/w 6 7 pa 0 r/w 7 port a data 7 to 0 these bits store data for port a pins 156 7.10.3 pin functions the port a pins are also used for tpc output (tp 7 to tp 0 ), itu input/output (tiocb 2 to tiocb 0 , tioca 2 to tioca 0 ), and input (tclkd, tclkc, tclkb, tclka). table 7-16 describes the selection of pin functions. table 7-16 port a pin functions pin pin functions and selection method pa 7 /tp 7 / itu channel 2 settings (bit pwm2 in tmdr and bits iob2 to iob0 in tior2), bit tiocb 2 nder7 in ndera, and bit pa 7 ddr in paddr select the pin function as follows itu channel 2 settings 1 in table below 2 in table below pa 7 ddr 0 1 1 nder7 0 1 pin function tiocb 2 output pa 7 pa 7 tp 7 input output output tiocb 2 input * note: * tiocb 2 input when iob2 = 1 and pwm2 = 0. itu channel 2 settings 21 2 iob2 0 1 iob1 0 0 1 iob0 0 1 157 table 7-16 port a pin functions (cont) pin pin functions and selection method itu channel 2 settings (bit pwm2 in tmdr and bits ioa2 to ioa0 in tior2), bit nder6 in ndera, and bit pa 6 ddr in paddr select the pin function as follows itu channel 2 settings 1 in table below 2 in table below pa 6 ddr 0 1 1 nder6 0 1 pin function tioca 2 output pa 6 input pa 6 output tp 6 output tioca 2 input * note: * tioca 2 input when ioa2 = 1. itu channel 2 settings 21 21 pwm2 0 1 ioa2 0 1 ioa1 0 0 1 ioa0 0 1 itu channel 1 settings (bit pwm1 in tmdr and bits iob2 to iob0 in tior1), bit nder5 in ndera, and bit pa 5 ddr in paddr select the pin function as follows itu channel 1 settings 1 in table below 2 in table below pa 5 ddr 0 1 1 nder5 0 1 pin function tiocb 1 output pa 5 input pa 5 output tp 5 output tiocb 1 input * note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. itu channel 1 settings 21 2 iob2 0 1 iob1 0 0 1 iob0 0 1 pa 6 /tp 6 / tioca 2 pa 5 /tp 5 / tiocb 1 158 table 7-16 port a pin functions (cont) pin pin functions and selection method itu channel 1 settings (bit pwm1 in tmdr and bits ioa2 to ioa0 in tior1), bit nder4 in ndera, and bit pa 4 ddr in paddr select the pin function as follows itu channel 1 settings 1 in table below 2 in table below pa 4 ddr 0 1 1 nder4 0 1 pin function tioca 1 output pa 4 input pa 4 output tp 4 output tioca 1 input * note: * tioca1 input when ioa2 = 1. itu channel 1 settings 21 21 pwm1 0 1 ioa2 0 1 ioa1 0 0 1 ioa0 0 1 itu channel 0 settings (bit pwm0 in tmdr and bits iob2 to iob0 in tior0), bits tpsc2 to tpsc0 in tcr4 to tcr0, bit nder3 in ndera, and bit pa 3 ddr in paddr select the pin function as follows itu channel 0 settings 1 in table below 2 in table below pa 3 ddr 0 1 1 nder3 0 1 pin function tiocb 0 output pa 3 input pa 3 output tp 3 output tiocb 0 input * 1 tclkd input * 2 notes: 1. tiocb 0 input when iob2 = 1 and pwm0 = 0. 2. tclkd input when tpsc2 = tpsc1 = tpsc0 = 1 in any of tcr4 to tcr0. itu channel 0 settings 21 2 iob2 0 1 iob1 0 0 1 iob0 0 1 pa 4 /tp 4 / tioca 1 pa 3 /tp 3 / tiocb 0 / tclkd 159 table 7-16 port a pin functions (cont) pin pin functions and selection method itu channel 0 settings (bit pwm0 in tmdr and bits ioa2 to ioa0 in tior0), bits tpsc2 to tpsc0 in tcr4 to tcr0, bit nder2 in ndera, and bit pa 2 ddr in paddr select the pin function as follows itu channel 0 settings 1 in table below 2 in table below pa 2 ddr 0 1 1 nder2 0 1 pin function tioca 0 output pa 2 input pa 2 output tp 2 output tioca 0 input * 1 tclkc input * 2 notes: 1. tioca 0 input when ioa2 = 1. 2. tclkc input when tpsc2 = tpsc1 = 1 and tpsc0 = 0 in any of tcr4 to tcr0. itu channel 0 settings 21 21 pwm0 0 1 ioa2 0 1 ioa1 0 0 1 ioa0 0 1 pa 2 /tp 2 / tioca 0 / tclkc 160 table 7-16 port a pin functions (cont) pin pin functions and selection method bit nder1 in ndera and bit pa 1 ddr in paddr select the pin function as follows pa 1 ddr 0 1 1 nder1 0 1 pin function pa 1 input pa 1 output tp 1 output tclkb input * note: * tclkb input when mdf = 1 in tmdr, or when tpsc2 = 1, tpsc1 = 0, and tpsc0 = 1 in any of tcr4 to tcr0. bit nder0 in ndera and bit pa 0 ddr in paddr select the pin function as follows pa 0 ddr 0 1 1 nder0 0 1 pin function pa 0 input pa 0 output tp 0 output tclka input * note: * tclka input when mdf = 1 in tmdr, or when tpsc2 = 1 and tpsc1 = 0 in any of tcr4 to tcr0. pa 1 /tp 1 / tclkb pa 0 /tp 0 / tclka 161 7.11 port b 7.11.1 overview port b is an 8-bit input/output port that is also used for tpc output (tp 15 to tp 8 ), itu input/output (tiocb 4 , tiocb 3 , tioca 4 , tioca 3 ) and itu output (tocxb 4 , tocxa 4 ), and adtrg input to the a/d converter. port b has the same set of pin functions in all operating modes. figure 7-20 shows the pin configuration of port b. pins in port b can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. pins pb 3 to pb 0 have schmitt-trigger inputs. figure 7-20 port b pin configuration 7.11.2 register descriptions table 7-17 summarizes the registers of port b. table 7-17 port b registers address * name abbreviation r/w initial value h'ffd4 port b data direction register pbddr w h'00 h'ffd6 port b data register pbdr r/w h'00 note: * lower 16 bits of the address. port b pb (input/output)/tp (output)/ adtrg (input) pb (input/output)/tp (output) pb (input/output)/tp (output)/tocxb (output) pb (input/output)/tp (output)/tocxa (output) 7 6 5 4 3 2 1 0 port b pins 15 14 13 12 11 10 9 8 4 4 pb (input/output)/tp (output)/tiocb (input/output) pb (input/output)/tp (output)/tioca (input/output) pb (input/output)/tp (output)/tiocb (input/output) pb (input/output)/tp (output)/tioca (input/output) 4 4 3 3 162 port b data direction register (pbddr): pbddr is an 8-bit write-only register that can select input or output for each pin in port b. a pin in port b becomes an output pin if the corresponding pbddr bit is set to 1, and an input pin if this bit is cleared to 0. pbddr is a write-only register. its value cannot be read. all bits return 1 when read. pbddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. if a pbddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port b data register (pbdr): pbdr is an 8-bit readable/writable register that stores data for pins pb7 to pb0. when a bit in pbddr is set to 1, if port b is read the value of the corresponding pbdr bit is returned directly. when a bit in pbddr is cleared to 0, if port b is read the corresponding pin level is read. pbdr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. when port b pins are used for tpc output, pbdr stores output data for tpc output groups 2 and 3. if a bit in the next data enable register (nderb) is set to 1, the corresponding pbdr bit cannot be written. in this case, pbdr can be updated only when data is transferred from ndrb. bit initial value read/write 7 pb ddr 0 w port b data direction 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 bit initial value read/write 0 pb 0 r/w 0 1 pb 0 r/w 1 2 pb 0 r/w 2 3 pb 0 r/w 3 4 pb 0 r/w 4 5 pb 0 r/w 5 6 pb 0 r/w 6 7 pb 0 r/w 7 port b data 7 to 0 these bits store data for port b pins 163 7.11.3 pin functions the port b pins are also used for tpc output (tp 15 to tp 8 ), itu input/output (tiocb 4 , tiocb 3 , tioca 4 , tioca 3 ) and output (tocxb 4 , tocxa 4 ), and adtrg input. table 7-18 describes the selection of pin functions. table 7-18 port b pin functions pin pin functions and selection method bit trge in adcr, bit nder15 in nderb and bit pb 7 ddr in pbddr select the pin function as follows pb 7 ddr 0 1 1 nder15 0 1 pin function pb 7 input pb 7 output tp 15 output adtrg input * notes: * adtrg input when trge = 1. bit nder14 in nderb and bit pb 6 ddr in pbddr select the pin function as follows pb 6 ddr 0 1 1 nder14 0 1 pin function pb 6 input pb 6 output tp 14 output itu channel 4 settings (bit cmd1 in tfcr and bit exb4 in toer), bit nder13 in nderb, and bit pb 5 ddr in pbddr select the pin function as follows exb4, cmd1 not both 1 both 1 pb 5 ddr 0 1 1 nder13 0 1 pin function pb 5 input pb 5 output tp 13 output tocxb 4 output itu channel 4 settings (bit cmd1 in tfcr and bit exa4 in toer), bit nder12 in nderb, and bit pb 4 ddr in pbddr select the pin function as follows exa4, cmd1 not both 1 both 1 pb 4 ddr 0 1 1 nder12 0 1 pin function pb 4 input pb 4 output tp 12 output tocxa 4 output pb 7 / tp 15 / adtrg pb 6 / tp 14 / pb 5 / tp 13 / tocxb 4 pb 4 / tp 12 / tocxa 4 164 table 7-18 port b pin functions (cont) pin pin functions and selection method itu channel 4 settings (bit pwm4 in tmdr, bit cmd1 in tfcr, bit eb4 in toer, and bits iob2 to iob0 in tior4), bit nder11 in nderb, and bit pb 3 ddr in pbddr select the pin function as follows itu channel 4 settings 1 in table below 2 in table below pb 3 ddr 0 1 1 nder11 0 1 pin function tiocb 4 output pb 3 input pb 3 output tp 11 output tiocb 4 input * note: * tiocb 4 input when cmd1 = pwm4 = 0 and iob2 = 1. itu channel 4 settings 22 1 21 eb4 0 1 cmd1 0 1 iob2 0001 iob1 0 0 1 iob0 0 1 pb 3 / tp 11 / tiocb 4 165 table 7-18 port b pin functions (cont) pin pin functions and selection method itu channel 4 settings (bit cmd1 in tfcr, bit ea4 in toer, bit pwm4 in tmdr, and bits ioa2 to ioa0 in tior4), bit nder10 in nderb, and bit pb 2 ddr in pbddr select the pin function as follows itu channel 4 settings 1 in table below 2 in table below pb 2 ddr 0 1 1 nder10 0 1 pin function tioca 4 output pb 2 input pb 2 output tp 10 output tioca 4 input * note: * tioca 4 input when cmd1 = pwm4 = 0 and ioa2 = 1. dmac channel 4 settings 22 1 2 1 ea4 0 1 cmd1 0 1 pwm4 0 1 ioa2 0 0 0 1 ioa1 0 0 1 ioa0 0 1 pb 2 / tp 10 / tioca 4 166 table 7-18 port b pin functions (cont) pin pin functions and selection method itu channel 3 settings (bit pwm3 in tmdr, bit cmd1 in tfcr, bit eb3 in toer, and bits iob2 to iob0 in tior3), bit nder9 in nderb, and bit pb 1 ddr in pbddr select the pin function as follows itu channel 3 settings 1 in table below 2 in table below pb 1 ddr 0 1 1 nder9 0 1 pin function tiocb 3 output pb 1 input pb 1 output tp 9 output tiocb 3 input * note: * tiocb 3 input when cmd1 = pwm3 = 0 and iob2 = 1. itu channel 3 settings 22 1 21 eb3 0 1 cmd1 0 1 iob2 0001 iob1 0 0 1 iob0 0 1 pb 1 /tp 9 / tiocb 3 167 table 7-18 port b pin functions (cont) pin pin functions and selection method itu channel 3 settings (bit cmd1 in tfcr, bit ea3 in toer, bit pwm3 in tmdr, and bits ioa2 to ioa0 in tior3), bit nder8 in nderb, and bit pb 0 ddr in pbddr select the pin function as follows itu channel 3 settings 1 in table below 2 in table below pb 0 ddr 0 1 1 nder8 0 1 pin function tioca 3 output pb 0 input pb 0 output tp 8 output tioca 3 input * note: * tioca3 input when cmd1 = pwm3 = 0 and ioa2 = 1. itu channel 3 settings 22 1 2 1 ea3 0 1 cmd1 0 1 pwm3 0 1 ioa2 0 0 0 1 ioa1 0 0 1 ioa0 0 1 pb 0 /tp 8 / tioca 3 168 section 8 16-bit integrated timer unit (itu) 8.1 overview the h8/3032 series has a built-in 16-bit integrated timer-pulse unit (itu) with five 16-bit timer channels. 8.1.1 features itu features are listed below. capability to process up to 12 pulse outputs or 10 pulse inputs ten general registers (grs, two per channel) with independently-assignable output compare or input capture functions selection of eight counter clock sources for each channel: internal clocks: ? ?2, ?4, ?8 external clocks: tclka, tclkb, tclkc, tclkd five operating modes selectable in all channels: waveform output by compare match selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) input capture function rising edge, falling edge, or both edges (selectable) counter clearing function counters can be cleared by compare match or input capture synchronization two or more timer counters (tcnts) can be preset simultaneously, or cleared simultaneously by compare match or input capture. counter synchronization enables synchronous register input and output. 169 pwm mode pwm output can be provided with an arbitrary duty cycle. with synchronization, up to five-phase pwm output is possible phase counting mode selectable in channel 2 two-phase encoder output can be counted automatically. three additional modes selectable in channels 3 and 4 reset-synchronized pwm mode if channels 3 and 4 are combined, three-phase pwm output is possible with three pairs of complementary waveforms. complementary pwm mode if channels 3 and 4 are combined, three-phase pwm output is possible with three pairs of non-overlapping complementary waveforms. buffering input capture registers can be double-buffered. output compare registers can be updated automatically. high-speed access via internal 16-bit bus the 16-bit timer counters, general registers, and buffer registers can be accessed at high speed via a 16-bit bus. fifteen interrupt sources each channel has two compare match/input capture interrupts and an overflow interrupt. all interrupts can be requested independently. output triggering of programmable pattern controller (tpc) compare match/input capture signals from channels 0 to 3 can be used as tpc output triggers. 170 table 8-1 summarizes the itu functions. table 8-1 itu functions item channel 0 channel 1 channel 2 channel 3 channel 4 clock sources internal clocks: ? ?2, ?4, ?8 external clocks: tclka, tclkb, tclkc, tclkd, selectable independently general registers gra0, grb0 gra1, grb1 gra2, grb2 gra3, grb3 gra4, grb4 (output compare/input capture registers) buffer registers bra3, brb3 bra4, brb4 input/output pins tioca 0 , tioca 1 , tioca 2 , tioca 3 , tioca 4 , tiocb 0 tiocb 1 tiocb 2 tiocb 3 tiocb 4 output pins t ocxa 4 , tocxb 4 counter clearing function gra0/grb0 gra1/grb1 gra2/grb2 gra3/grb3 gra4/grb4 compare compare compare compare compare match or match or match or match or match or input capture input capture input capture input capture input capture 0 oo oo o 1 oo oo o toggle oo oo input capture function oo oo o synchronization oo oo o pwm mode oo oo o reset-synchronized oo pwm mode complementary pwm oo mode phase counting mode o buffering oo interrupt sources three sources three sources three sources three sources three sources ? compare ? compare ? compare ? compare ? compare match/input match/input match/input match/input match/input capture a0 capture a1 capture a2 capture a3 capture a4 ? compare ? compare ? compare ? compare ? compare match/input match/input match/input match/input match/input capture b0 capture b1 capture b2 capture b3 capture b4 ? overflow ? overflow ? overflow ? overflow ? overflow legend o : available : not available compare match output 171 8.1.2 block diagrams itu block diagram (overall): figure 8-1 is a block diagram of the itu. figure 8-1 itu block diagram (overall) 16-bit timer channel 4 16-bit timer channel 3 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 module data bus bus interface on-chi p data bus imia0 to imia4 imib0 to imib4 ovi0 to ovi4 tclka to tclkd ? ?2, ?4, ?8 tocxa 4 , tocxb 4 clock selector control logic counter control and pulse i/o control unit tioca 0 to tioca 4 tiocb 0 to tiocb 4 todr tocr tstr tsnc tmdr tfcr toer: tocr: tstr: tsnc: tmdr: tfcr: legend timer output master enable register (8 bits) timer output control register (8 bits) timer start register (8 bits) timer synchro register (8 bits) timer mode register (8 bits) timer function control register (8 bits) 172 block diagram of channels 0 and 1: itu channels 0 and 1 are functionally identical. both have the structure shown in figure 8-2. figure 8-2 block diagram of channels 0 and 1 (for channel 0) clock selector comparator control logic tclka to tclkd ? ?2, ?4, ?8 tioca 0 tiocb 0 imia0 imib0 ovi0 tcnt gra grb tcr tior tier tsr module data bus legend tcnt: gra, grb: tcr: tior: tier: tsr: timer counter (16 bits) general registers a and b (input capture/output compare registers) (16 bits 2) timer control register (8 bits) timer i/o control register (8 bits) timer interrupt enable register (8 bits) timer status register (8 bits) 173 block diagram of channel 2: figure 8-3 is a block diagram of channel 2. this is the channel that provides only 0 output and 1 output. figure 8-3 block diagram of channel 2 clock selector comparator control logic tclka to tclkd ? ?2, ?4, ?8 tioca 2 tiocb 2 imia2 imib2 ovi2 tcnt2 gra2 grb2 tcr2 tior2 tier2 tsr2 module data bus legend tcnt2: gra2, grb2: tcr2: tior2: tier2: tsr2: timer counter 2 (16 bits) general registers a2 and b2 (input capture/output compare registers) (16 bits 2) timer control register 2 (8 bits) timer i/o control register 2 (8 bits) timer interrupt enable register 2 (8 bits) timer status register 2 (8 bits) 174 block diagrams of channels 3 and 4: figure 8-4 is a block diagram of channel 3. figure 8-5 is a block diagram of channel 4. figure 8-4 block diagram of channel 3 tcnt3 bra3 legend tcnt3: gra3, grb3: bra3, brb3: tcr3: tior3: tier3: tsr3: timer counter 3 (16 bits) general registers a3 and b3 (input capture/output compare registers) (16 bits 2) buffer registers a3 and b3 (input capture/output compare buffer registers) (16 bits 2) timer control register 3 (8 bits) clock selector comparator control logic gra3 brb3 grb3 tcr3 tior3 tier3 tsr3 tclka to tclkd ? ?2, ?4, ?8 tioca 3 tiocb 3 module data bus imia3 imib3 ovi3 timer i/o control register 3 (8 bits) timer interrupt enable register 3 (8 bits) timer status register 3 (8 bits) 175 figure 8-5 block diagram of channel 4 tcnt4 bra4 legend tcnt4: gra4, grb4: bra4, brb4: tcr4: tior4: tier4: tsr4: timer counter 4 (16 bits) general registers a4 and b4 (input capture/output compare registers) (16 bits 2) buffer registers a4 and b4 (input capture/output compare buffer registers) (16 bits 2) timer control register 4 (8 bits) clock selector comparator control logic gra4 brb4 grb4 tcr4 tior4 tier4 tsr4 module data bus tclka to tclkd ? ?2, ?4, ?8 timer i/o control register 4 (8 bits) timer interrupt enable register 4 (8 bits) timer status register 4 (8 bits) tocxa 4 tocxb 4 tioca 4 tiocb 4 imia4 imib4 ovi4 176 8.1.3 input/output pins table 8-2 summarizes the itu pins. table 8-2 itu pins abbre- input/ channel name viation output function common clock input a tclka input external clock a input pin (phase-a input pin in phase counting mode) clock input b tclkb input external clock b input pin (phase-b input pin in phase counting mode) clock input c tclkc input external clock c input pin clock input d tclkd input external clock d input pin 0 input capture/output tioca 0 input/ gra0 output compare or input capture pin compare a0 output pwm output pin in pwm mode input capture/output tiocb 0 input/ grb0 output compare or input capture pin compare b0 output 1 input capture/output tioca 1 input/ gra1 output compare or input capture pin compare a1 output pwm output pin in pwm mode input capture/output tiocb 1 input/ grb1 output compare or input capture pin compare b1 output 2 input capture/output tioca 2 input/ gra2 output compare or input capture pin compare a2 output pwm output pin in pwm mode input capture/output tiocb 2 input/ grb2 output compare or input capture pin compare b2 output 3 input capture/output tioca 3 input/ gra3 output compare or input capture pin compare a3 output pwm output pin in pwm mode, comple- mentary pwm mode, or reset-synchronized pwm mode input capture/output tiocb 3 input/ grb3 output compare or input capture pin compare b3 output pwm output pin in complementary pwm mode or reset-synchronized pwm mode 4 input capture/output tioca 4 input/ gra4 output compare or input capture pin compare a4 output pwm output pin in pwm mode, comple- mentary pwm mode, or reset-synchronized pwm mode input capture/output tiocb 4 input/ grb4 output compare or input capture pin compare b4 output pwm output pin in complementary pwm mode or reset-synchronized pwm mode output compare xa4 tocxa 4 output pwm output pin in complementary pwm mode or reset-synchronized pwm mode output compare xb4 tocxb 4 output pwm output pin in complementary pwm mode or reset-synchronized pwm mode 177 8.1.4 register configuration table 8-3 summarizes the itu registers. table 8-3 itu registers abbre- initial channel address * 1 name viation r/w value common h'ff60 timer start register tstr r/w h'e0 h'ff61 timer synchro register tsnc r/w h'e0 h'ff62 timer mode register tmdr r/w h'80 h'ff63 timer function control register tfcr r/w h'c0 h'ff90 timer output master enable register toer r/w h'ff h'ff91 timer output control register tocr r/w h'ff 0 h'ff64 timer control register 0 tcr0 r/w h'80 h'ff65 timer i/o control register 0 tior0 r/w h'88 h'ff66 timer interrupt enable register 0 tier0 r/w h'f8 h'ff67 timer status register 0 tsr0 r/(w) * 2 h'f8 h'ff68 timer counter 0 (high) tcnt0h r/w h'00 h'ff69 timer counter 0 (low) tcnt0l r/w h'00 h'ff6a general register a0 (high) gra0h r/w h'ff h'ff6b general register a0 (low) gra0l r/w h'ff h'ff6c general register b0 (high) grb0h r/w h'ff h'ff6d general register b0 (low) grb0l r/w h'ff 1 h'ff6e timer control register 1 tcr1 r/w h'80 h'ff6f timer i/o control register 1 tior1 r/w h'88 h'ff70 timer interrupt enable register 1 tier1 r/w h'f8 h'ff71 timer status register 1 tsr1 r/(w) * 2 h'f8 h'ff72 timer counter 1 (high) tcnt1h r/w h'00 h'ff73 timer counter 1 (low) tcnt1l r/w h'00 h'ff74 general register a1 (high) gra1h r/w h'ff h'ff75 general register a1 (low) gra1l r/w h'ff h'ff76 general register b1 (high) grb1h r/w h'ff h'ff77 general register b1 (low) grb1l r/w h'ff notes: 1. the lower 16 bits of the address are indicated. 2. only 0 can be written, to clear flags. 178 table 8-3 itu registers (cont) abbre- initial channel address * 1 name viation r/w value 2 h'ff78 timer control register 2 tcr2 r/w h'80 h'ff79 timer i/o control register 2 tior2 r/w h'88 h'ff7a timer interrupt enable register 2 tier2 r/w h'f8 h'ff7b timer status register 2 tsr2 r/(w) * 2 h'f8 h'ff7c timer counter 2 (high) tcnt2h r/w h'00 h'ff7d timer counter 2 (low) tcnt2l r/w h'00 h'ff7e general register a2 (high) gra2h r/w h'ff h'ff7f general register a2 (low) gra2l r/w h'ff h'ff80 general register b2 (high) grb2h r/w h'ff h'ff81 general register b2 (low) grb2l r/w h'ff 3 h'ff82 timer control register 3 tcr3 r/w h'80 h'ff83 timer i/o control register 3 tior3 r/w h'88 h'ff84 timer interrupt enable register 3 tier3 r/w h'f8 h'ff85 timer status register 3 tsr3 r/(w) * 2 h'f8 h'ff86 timer counter 3 (high) tcnt3h r/w h'00 h'ff87 timer counter 3 (low) tcnt3l r/w h'00 h'ff88 general register a3 (high) gra3h r/w h'ff h'ff89 general register a3 (low) gra3l r/w h'ff h'ff8a general register b3 (high) grb3h r/w h'ff h'ff8b general register b3 (low) grb3l r/w h'ff h'ff8c buffer register a3 (high) bra3h r/w h'ff h'ff8d buffer register a3 (low) bra3l r/w h'ff h'ff8e buffer register b3 (high) brb3h r/w h'ff h'ff8f buffer register b3 (low) brb3l r/w h'ff notes: 1. the lower 16 bits of the address are indicated. 2. only 0 can be written, to clear flags. 179 table 8-3 itu registers (cont) abbre- initial channel address * 1 name viation r/w value 4 h'ff92 timer control register 4 tcr4 r/w h'80 h'ff93 timer i/o control register 4 tior4 r/w h'88 h'ff94 timer interrupt enable register 4 tier4 r/w h'f8 h'ff95 timer status register 4 tsr4 r/(w) * 2 h'f8 h'ff96 timer counter 4 (high) tcnt4h r/w h'00 h'ff97 timer counter 4 (low) tcnt4l r/w h'00 h'ff98 general register a4 (high) gra4h r/w h'ff h'ff99 general register a4 (low) gra4l r/w h'ff h'ff9a general register b4 (high) grb4h r/w h'ff h'ff9b general register b4 (low) grb4l r/w h'ff h'ff9c buffer register a4 (high) bra4h r/w h'ff h'ff9d buffer register a4 (low) bra4l r/w h'ff h'ff9e buffer register b4 (high) brb4h r/w h'ff h'ff9f buffer register b4 (low) brb4l r/w h'ff notes: 1. the lower 16 bits of the address are indicated. 2. only 0 can be written, to clear flags. 180 8.2 register descriptions 8.2.1 timer start register (tstr) tstr is an 8-bit readable/writable register that starts and stops the timer counter (tcnt) in channels 0 to 4. tstr is initialized to h'e0 by a reset and in standby mode. bits 7 to 5?eserved: read-only bits, always read as 1. bit 4?ounter start 4 (str4): starts and stops timer counter 4 (tcnt4). bit 4 str4 description 0 tcnt4 is halted (initial value) 1 tcnt4 is counting bit 3?ounter start 3 (str3): starts and stops timer counter 3 (tcnt3). bit 3 str3 description 0 tcnt3 is halted (initial value) 1 tcnt3 is counting bit 2?ounter start 2 (str2): starts and stops timer counter 2 (tcnt2). bit 2 str2 description 0 tcnt2 is halted (initial value) 1 tcnt2 is counting bit initial value read/write 7 1 6 1 5 1 4 str4 0 r/w 3 str3 0 r/w 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w reserved bits counter start 4 to 0 these bits start and stop tcnt4 to tcnt0 181 bit 1?ounter start 1 (str1): starts and stops timer counter 1 (tcnt1). bit 1 str1 description 0 tcnt1 is halted (initial value) 1 tcnt1 is counting bit 0?ounter start 0 (str0): starts and stops timer counter 0 (tcnt0). bit 0 str0 description 0 tcnt0 is halted (initial value) 1 tcnt0 is counting 8.2.2 timer synchro register (tsnc) tsnc is an 8-bit readable/writable register that selects whether channels 0 to 4 operate independently or synchronously. channels are synchronized by setting the corresponding bits to 1. tsnc is initialized to h'e0 by a reset and in standby mode. bits 7 to 5?eserved: read-only bits, always read as 1. bit 4?imer sync 4 (sync4): selects whether channel 4 operates independently or synchronously. bit 4 sync4 description 0 channel 4 s timer counter (tcnt4) operates independently (initial value) tcnt4 is preset and cleared independently of other channels 1 channel 4 operates synchronously tcnt4 can be synchronously preset and cleared bit initial value read/write 7 1 6 1 5 1 4 sync4 0 r/w 3 sync3 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w reserved bits timer sync 4 to 0 these bits synchronize channels 4 to 0 182 bit 3?imer sync 3 (sync3): selects whether channel 3 operates independently or synchronously. bit 3 sync3 description 0 channel 3 s timer counter (tcnt3) operates independently (initial value) tcnt3 is preset and cleared independently of other channels 1 channel 3 operates synchronously tcnt3 can be synchronously preset and cleared bit 2?imer sync 2 (sync2): selects whether channel 2 operates independently or synchronously. bit 2 sync2 description 0 channel 2 s timer counter (tcnt2) operates independently (initial value) tcnt2 is preset and cleared independently of other channels 1 channel 2 operates synchronously tcnt2 can be synchronously preset and cleared bit 1?imer sync 1 (sync1): selects whether channel 1 operates independently or synchronously. bit 1 sync1 description 0 channel 1 s timer counter (tcnt1) operates independently (initial value) tcnt1 is preset and cleared independently of other channels 1 channel 1 operates synchronously tcnt1 can be synchronously preset and cleared bit 0?imer sync 0 (sync0): selects whether channel 0 operates independently or synchronously. bit 0 sync0 description 0 channel 0 s timer counter (tcnt0) operates independently (initial value) tcnt0 is preset and cleared independently of other channels 1 channel 0 operates synchronously tcnt0 can be synchronously preset and cleared 183 8.2.3 timer mode register (tmdr) tmdr is an 8-bit readable/writable register that selects pwm mode for channels 0 to 4. it also selects phase counting mode and the overflow flag (ovf) setting conditions for channel 2. tmdr is initialized to h'80 by a reset and in standby mode. bit 7?eserved: read-only bit, always read as 1. bit 6?hase counting mode flag (mdf): selects whether channel 2 operates normally or in phase counting mode. bit 6 mdf description 0 channel 2 operates normally (initial value) 1 channel 2 operates in phase counting mode bit initial value read/write 7 1 6 mdf 0 r/w 5 fdir 0 r/w 4 pwm4 0 r/w 3 pwm3 0 r/w 0 pwm0 0 r/w 2 pwm2 0 r/w 1 pwm1 0 r/w reserved bit pwm mode 4 to 0 these bits select pwm mode for channels 4 to 0 phase counting mode flag selects phase counting mode for channel 2 flag direction selects the setting condition for the overflow flag (ovf) in timer status register 2 (tsr2) 184 when mdf is set to 1 to select phase counting mode, timer counter 2 (tcnt2) operates as an up/down-counter and pins tclka and tclkb become counter clock input pins. tcnt2 counts both rising and falling edges of tclka and tclkb, and counts up or down as follows. counting direction down-counting up-counting tclka pin high low low high tclkb pin low high high low in phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits ckeg1 and ckeg0 and the clock source selected by bits tpsc2 to tpsc0 in timer control register 2 (tcr2). phase counting mode takes precedence over these settings. the counter clearing condition selected by the cclr1 and cclr0 bits in tcr2 and the compare match/input capture settings and interrupt functions of timer i/o control register 2 (tior2), timer interrupt enable register 2 (tier2), and timer status register 2 (tsr2) remain effective in phase counting mode. bit 5?lag direction (fdir): designates the setting condition for the overflow flag (ovf) in timer status register 2 (tsr2). the fdir designation is valid in all modes in channel 2. bit 5 fdir description 0 ovf is set to 1 in tsr2 when tcnt2 overflows or underflows (initial value) 1 ovf is set to 1 in tsr2 when tcnt2 overflows bit 4?wm mode 4 (pwm4): selects whether channel 4 operates normally or in pwm mode. bit 4 pwm4 description 0 channel 4 operates normally (initial value) 1 channel 4 operates in pwm mode when bit pwm4 is set to 1 to select pwm mode, pin tioca4 becomes a pwm output pin. the output goes to 1 at compare match with general register a4 (gra4), and to 0 at compare match with general register b4 (grb4). if complementary pwm mode or reset-synchronized pwm mode is selected by bits cmd1 and cmd0 in the timer function control register (tfcr), the cmd1 and cmd0 setting takes precedence and the pwm4 setting is ignored. 185 bit 3?wm mode 3 (pwm3): selects whether channel 3 operates normally or in pwm mode. bit 3 pwm3 description 0 channel 3 operates normally (initial value) 1 channel 3 operates in pwm mode when bit pwm3 is set to 1 to select pwm mode, pin tioca3 becomes a pwm output pin. the output goes to 1 at compare match with general register a3 (gra3), and to 0 at compare match with general register b3 (grb3). if complementary pwm mode or reset-synchronized pwm mode is selected by bits cmd1 and cmd0 in the timer function control register (tfcr), the cmd1 and cmd0 setting takes precedence and the pwm3 setting is ignored. bit 2?wm mode 2 (pwm2): selects whether channel 2 operates normally or in pwm mode. bit 2 pwm2 description 0 channel 2 operates normally (initial value) 1 channel 2 operates in pwm mode when bit pwm2 is set to 1 to select pwm mode, pin tioca2 becomes a pwm output pin. the output goes to 1 at compare match with general register a2 (gra2), and to 0 at compare match with general register b2 (grb2). bit 1?wm mode 1 (pwm1): selects whether channel 1 operates normally or in pwm mode. bit 1 pwm1 description 0 channel 1 operates normally (initial value) 1 channel 1 operates in pwm mode when bit pwm1 is set to 1 to select pwm mode, pin tioca1 becomes a pwm output pin. the output goes to 1 at compare match with general register a1 (gra1), and to 0 at compare match with general register b1 (grb1). 186 bit 0?wm mode 0 (pwm0): selects whether channel 0 operates normally or in pwm mode. bit 0 pwm0 description 0 channel 0 operates normally (initial value) 1 channel 0 operates in pwm mode when bit pwm0 is set to 1 to select pwm mode, pin tioca0 becomes a pwm output pin. the output goes to 1 at compare match with general register a0 (gra0), and to 0 at compare match with general register b0 (grb0). 8.2.4 timer function control register (tfcr) tfcr is an 8-bit readable/writable register that selects complementary pwm mode, reset- synchronized pwm mode, and buffering for channels 3 and 4. tfcr is initialized to h'c0 by a reset and in standby mode. bits 7 and 6?eserved: read-only bits, always read as 1. bit initial value read/write 7 1 6 1 5 cmd1 0 r/w 4 cmd0 0 r/w 3 bfb4 0 r/w 0 bfa3 0 r/w 2 bfa4 0 r/w 1 bfb3 0 r/w reserved bits combination mode 1/0 these bits select complementary pwm mode or reset-synchronized pwm mode for channels 3 and 4 buffer mode b4 and a4 these bits select buffering of general registers (grb4 and gra4) by buffer registers (brb4 and bra4) in channel 4 buffer mode b3 and a3 these bits select buffering of general registers (grb3 and gra3) by buffer registers (brb3 and bra3) in channel 3 187 bits 5 and 4?ombination mode 1 and 0 (cmd1, cmd0): these bits select whether channels 3 and 4 operate in normal mode, complementary pwm mode, or reset-synchronized pwm mode. bit 5 bit 4 cmd1 cmd0 description 0 0 channels 3 and 4 operate normally (initial value) 1 1 0 channels 3 and 4 operate together in complementary pwm mode 1 channels 3 and 4 operate together in reset-synchronized pwm mode before selecting reset-synchronized pwm mode or complementary pwm mode, halt the timer counter or counters that will be used in these modes. when these bits select complementary pwm mode or reset-synchronized pwm mode, they take precedence over the setting of the pwm mode bits (pwm4 and pwm3) in tmdr. settings of timer sync bits sync4 and sync3 in the timer synchro register (tsnc) are valid in complementary pwm mode and reset-synchronized pwm mode, however. when complementary pwm mode is selected, channels 3 and 4 must not be synchronized (do not set bits sync3 and sync4 both to 1 in tsnc). bit 3?uffer mode b4 (bfb4): selects whether grb4 operates normally in channel 4, or whether grb4 is buffered by brb4. bit 3 bfb4 description 0 grb4 operates normally (initial value) 1 grb4 is buffered by brb4 bit 2?uffer mode a4 (bfa4): selects whether gra4 operates normally in channel 4, or whether gra4 is buffered by bra4. bit 2 bfa4 description 0 gra4 operates normally (initial value) 1 gra4 is buffered by bra4 188 bit 1?uffer mode b3 (bfb3): selects whether grb3 operates normally in channel 3, or whether grb3 is buffered by brb3. bit 1 bfb3 description 0 grb3 operates normally (initial value) 1 grb3 is buffered by brb3 bit 0?uffer mode a3 (bfa3): selects whether gra3 operates normally in channel 3, or whether gra3 is buffered by bra3. bit 0 bfa3 description 0 gra3 operates normally (initial value) 1 gra3 is buffered by bra3 8.2.5 timer output master enable register (toer) toer is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. toer is initialized to h'ff by a reset and in standby mode. bits 7 and 6?eserved: read-only bits, always read as 1. bit initial value read/write 7 ? 1 6 ? 1 5 exb4 1 r/w 4 exa4 1 r/w 3 eb3 1 r/w 0 ea3 1 r/w 2 eb4 1 r/w 1 ea4 1 r/w reserved bits master enable tocxa 4 , tocxb 4 these bits enable or disable output settings for pins tocxa4 and tocxb4 master enable tioca 3 , tiocb 3 , tioca 4 , tiocb 4 these bits enable or disable output settings for pins tioca3, tiocb3 , tioca4, and tiocb4 189 bit 5?aster enable tocxb 4 (exb4): enables or disables itu output at pin tocxb 4 . bit 5 exb4 description 0 tocxb 4 output is disabled regardless of tfcr settings (tocxb 4 operates as a generic input/output pin). if xtgd = 0, exb4 is cleared to 0 when input capture a occurs in channel 1. 1 tocxb 4 is enabled for output according to tfcr settings (initial value) bit 4?aster enable tocxa 4 (exa4): enables or disables itu output at pin tocxa 4 . bit 4 exa4 description 0 tocxa 4 output is disabled regardless of tfcr settings (tocxa 4 operates as a generic input/output pin). if xtgd = 0, exa4 is cleared to 0 when input capture a occurs in channel 1. 1 tocxa 4 is enabled for output according to tfcr settings (initial value) bit 3?aster enable tiocb 3 (eb3): enables or disables itu output at pin tiocb 3 . bit 3 eb3 description 0 tiocb 3 output is disabled regardless of tior3 and tfcr settings (tiocb 3 operates as a generic input/output pin). if xtgd = 0, eb3 is cleared to 0 when input capture a occurs in channel 1. 1 tiocb 3 is enabled for output according to tior3 and tfcr settings (initial value) 190 bit 2?aster enable tiocb 4 (eb4): enables or disables itu output at pin tiocb 4 . bit 2 eb4 description 0 tiocb 4 output is disabled regardless of tior4 and tfcr settings (tiocb 4 operates as a generic input/output pin). if xtgd = 0, eb4 is cleared to 0 when input capture a occurs in channel 1. 1 tiocb 4 is enabled for output according to tior4 and tfcr settings (initial value) bit 1?aster enable tioca 4 (ea4): enables or disables itu output at pin tioca 4 . bit 1 ea4 description 0 tioca 4 output is disabled regardless of tior4, tmdr, and tfcr settings (tioca 4 operates as a generic input/output pin). if xtgd = 0, ea4 is cleared to 0 when input capture a occurs in channel 1. 1 tioca 4 is enabled for output according to tior4, tmdr, and (initial value) tfcr settings bit 0?aster enable tioca 3 (ea3): enables or disables itu output at pin tioca 3 . bit 0 ea3 description 0 tioca 3 output is disabled regardless of tior3, tmdr, and tfcr settings (tioca 3 operates as a generic input/output pin). if xtgd = 0, ea3 is cleared to 0 when input capture a occurs in channel 1. 1 tioca 3 is enabled for output according to tior3, tmdr, and (initial value) tfcr settings 191 8.2.6 timer output control register (tocr) tocr is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary pwm mode and reset-synchronized pwm mode, and inverts the output levels. the settings of the xtgd, ols4, and ols3 bits are valid only in complementary pwm mode and reset-synchronized pwm mode. these settings do not affect other modes. tocr is initialized to h'ff by a reset and in standby mode. bits 7 to 5?eserved: read-only bits, always read as 1. bit 4?xternal trigger disable (xtgd): selects externally triggered disabling of itu output in complementary pwm mode and reset-synchronized pwm mode. bit 4 xtgd description 0 input capture a in channel 1 is used as an external trigger signal in complementary pwm mode and reset-synchronized pwm mode. when an external trigger occurs, bits 5 to 0 in the timer output master enable register (toer) are cleared to 0, disabling itu output. 1 external triggering is disabled (initial value) bit initial value read/write 7 1 6 1 5 1 4 xtgd 1 r/w 3 1 0 ols3 1 r/w 2 1 1 ols4 1 r/w reserved bits output level select 3, 4 these bits select output levels in complementary pwm mode and reset- synchronized pwm mode external trigger disable selects externally triggered disabling of output in complementary pwm mode and reset-synchronized pwm mode reserved bits 192 bits 3 and 2?eserved: read-only bits, always read as 1. bit 1?utput level select 4 (ols4): selects output levels in complementary pwm mode and reset-synchronized pwm mode. bit 1 ols4 description 0 tioca3, tioca4, and tiocb4 outputs are inverted 1 tioca3, tioca4, and tiocb4 outputs are not inverted (initial value) bit 0?utput level select 3 (ols3): selects output levels in complementary pwm mode and reset-synchronized pwm mode. bit 0 ols3 description 0 tiocb3, tocxa4, and tocxb4 outputs are inverted 1 tiocb3, tocxa4, and tocxb4 outputs are not inverted (initial value) 8.2.7 timer counters (tcnt) tcnt is a 16-bit counter. the itu has five tcnts, one for each channel. channel abbreviation function 0 tcnt0 up-counter 1 tcnt1 2 tcnt2 phase counting mode: up/down-counter other modes: up-counter 3 tcnt3 4 tcnt4 each tcnt is a 16-bit readable/writable register that counts pulse inputs from a clock source. the clock source is selected by bits tpsc2 to tpsc0 in the timer control register (tcr). bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w complementary pwm mode: up/down-counter other modes: up-counter 193 tcnt0 and tcnt1 are up-counters. tcnt2 is an up/down-counter in phase counting mode and an up-counter in other modes. tcnt3 and tcnt4 are up/down-counters in complementary pwm mode and up-counters in other modes. tcnt can be cleared to h'0000 by compare match with general register a or b (gra or grb) or by input capture to gra or grb (counter clearing function) in the same channel. when tcnt overflows (changes from h'ffff to h'0000), the overflow flag (ovf) is set to 1 in the timer status register (tsr) of the corresponding channel. when tcnt underflows (changes from h'0000 to h'ffff), the overflow flag (ovf) is set to 1 in tsr of the corresponding channel. the tcnts are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. each tcnt is initialized to h'0000 by a reset and in standby mode. 8.2.8 general registers (gra, grb) the general registers are 16-bit registers. the itu has 10 general registers, two in each channel. channel abbreviation function 0 gra0, grb0 output compare/input capture register 1 gra1, grb1 2 gra2, grb2 3 gra3, grb3 4 gra4, grb4 a general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. the function is selected by settings in the timer i/o control register (tior). when a general register is used as an output compare register, its value is constantly compared with the tcnt value. when the two values match (compare match), the imfa or imfb flag is set to 1 in the timer status register (tsr). compare match output can be selected in tior. output compare/input capture register; can be buffered by buffer registers bra and brb bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w 194 when a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current tcnt value is stored in the general register. the corresponding imfa or imfb flag in tsr is set to 1 at the same time. the valid edge or edges of the input capture signal are selected in tior. tior settings are ignored in pwm mode, complementary pwm mode, and reset-synchronized pwm mode. general registers are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. general registers are initialized to the output compare function (with no output signal) by a reset and in standby mode. the initial value is h'ffff. 8.2.9 buffer registers (bra, brb) the buffer registers are 16-bit registers. the itu has four buffer registers, two each in channels 3 and 4. channel abbreviation function 3 bra3, brb3 used for buffering 4 bra4, brb4 when the corresponding gra or grb functions as an output compare register, bra or brb can function as an output compare buffer register: the bra or brb value is automatically transferred to gra or grb at compare match when the corresponding gra or grb functions as an input capture register, bra or brb can function as an input capture buffer register: the gra or grb value is automatically transferred to bra or brb at input capture a buffer register is a 16-bit readable/writable register that is used when buffering is selected. buffering can be selected independently by bits bfb4, bfa4, bfb3, and bfa3 in tfcr. the buffer register and general register operate as a pair. when the general register functions as an output compare register, the buffer register functions as an output compare buffer register. when the general register functions as an input capture register, the buffer register functions as an input capture buffer register. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w 195 the buffer registers are linked to the cpu by an internal 16-bit bus and can be written or read by either word or byte access. buffer registers are initialized to h'ffff by a reset and in standby mode. 8.2.10 timer control registers (tcr) tcr is an 8-bit register. the itu has five tcrs, one in each channel. channel abbreviation function 0 tcr0 1 tcr1 2 tcr2 3 tcr3 4 tcr4 each tcr is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. tcr is initialized to h'80 by a reset and in standby mode. bit 7?eserved: read-only bit, always read as 1. tcr controls the timer counter. the tcrs in all channels are functionally identical. when phase counting mode is selected in channel 2, the settings of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in tcr2 are ignored. bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w timer prescaler 2 to 0 these bits select the counter clock reserved bit clock edge 1/0 these bits select external clock edges counter clear 1/0 these bits select the counter clear source 196 bits 6 and 5?ounter clear 1/0 (cclr1, cclr0): these bits select how tcnt is cleared. bit 6 bit 5 cclr1 cclr0 description 0 0 tcnt is not cleared (initial value) 1 tcnt is cleared by gra compare match or input capture * 1 1 0 tcnt is cleared by grb compare match or input capture * 1 1 synchronous clear: tcnt is cleared in synchronization with other synchronized timers * 2 notes: 1. tcnt is cleared by compare match when the general register functions as a compare match register, and by input capture when the general register functions as an input capture register. 2. selected in the timer synchro register (tsnc). bits 4 and 3?lock edge 1/0 (ckeg1, ckeg0): these bits select external clock input edges when an external clock source is used. bit 4 bit 3 ckeg1 ckeg0 description 0 0 count rising edges (initial value) 1 count falling edges 1 count both edges when channel 2 is set to phase counting mode, bits ckeg1 and ckeg0 in tcr2 are ignored. phase counting takes precedence. 197 bits 2 to 0?imer prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the counter clock source. bit 2 bit 1 bit 0 tpsc2 tpsc1 tpsc0 function 0 0 0 internal clock: (initial value) 1 internal clock: ?2 1 0 internal clock: ?4 1 internal clock: ?8 1 0 0 external clock a: tclka input 1 external clock b: tclkb input 1 0 external clock c: tclkc input 1 external clock d: tclkd input when bit tpsc2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. when bit tpsc2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits ckeg1 and ckeg0. when channel 2 is set to phase counting mode (mdf = 1 in tmdr), the settings of bits tpsc2 to tpsc0 in tcr2 are ignored. phase counting takes precedence. 8.2.11 timer i/o control register (tior) tior is an 8-bit register. the itu has five tiors, one in each channel. channel abbreviation function 0 tior0 1 tior1 2 tior2 3 tior3 4 tior4 tior controls the general registers. some functions differ in pwm mode. tior3 and tior4 settings are ignored when complementary pwm mode or reset-synchronized pwm mode is selected in channels 3 and 4. 198 each tior is an 8-bit readable/writable register that selects the output compare or input capture function for gra and grb, and specifies the functions of the tioca and tiocb pins. if the output compare function is selected, tior also selects the type of output. if input capture is selected, tior also selects the edge or edges of the input capture signal. tior is initialized to h'88 by a reset and in standby mode. bit 7?eserved: read-only bit, always read as 1. bits 6 to 4?/o control b2 to b0 (iob2 to iob0): these bits select the grb function. bit 6 bit 5 bit 4 iob2 iob1 iob0 function 0 0 0 no output at compare match (initial value) 1 0 output at grb compare match * 1 1 0 1 output at grb compare match * 1 1 output toggles at grb compare match (1 output in channel 2) * 1, * 2 1 0 0 grb captures rising edge of input 1 grb captures falling edge of input 1 0 grb captures both edges of input 1 notes: 1. after a reset, the output is 0 until the first compare match. 2. channel 2 output cannot be toggled by compare match. this setting selects 1 output instead. bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w i/o control a2 to a0 these bits select gra functions reserved bit i/o control b2 to b0 these bits select grb functions reserved bit grb is an output compare register grb is an input capture register 199 bit 3?eserved: read-only bit, always read as 1. bits 2 to 0?/o control a2 to a0 (ioa2 to ioa0): these bits select the gra function. bit 2 bit 1 bit 0 ioa2 ioa1 ioa0 function 0 0 0 no output at compare match (initial value) 1 0 output at gra compare match * 1 1 0 1 output at gra compare match * 1 1 output toggles at gra compare match (1 output in channel 2) * 1, * 2 1 0 0 gra captures rising edge of input 1 gra captures falling edge of input 1 0 gra captures both edges of input 1 notes: 1. after a reset, the output is 0 until the first compare match. 2. channel 2 output cannot be toggled by compare match. this setting selects 1 output instead. 8.2.12 timer status register (tsr) tsr is an 8-bit register. the itu has five tsrs, one in each channel. channel abbreviation function 0 tsr0 indicates input capture, compare match, and overflow status 1 tsr1 2 tsr2 3 tsr3 4 tsr4 gra is an output compare register gra is an input capture register 200 each tsr is an 8-bit readable/writable register containing flags that indicate tcnt overflow or underflow and gra or grb compare match or input capture. these flags are interrupt sources and generate cpu interrupts if enabled by corresponding bits in the timer interrupt enable register (tier). tsr is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?eserved: read-only bits, always read as 1. bit 2?verflow flag (ovf): this status flag indicates tcnt overflow or underflow. bit 2 ovf description 0 [clearing condition] (initial value) read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff * notes: * tcnt underflow occurs when tcnt operates as an up/down-counter. underflow occurs only under the following conditions: 1. channel 2 operates in phase counting mode (mdf = 1 in tmdr) 2. channels 3 and 4 operate in complementary pwm mode (cmd1 = 1 and cmd0 = 0 in tfcr) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 * 2 ovf 0 r/(w) reserved bits note: only 0 can be written, to clear the flag. * * 1 imfb 0 r/(w) * 0 imfa 0 r/(w) overflow flag status flag indicating overflow or underflow input capture/compare match flag b status flag indicating grb compare match or input capture input capture/compare match flag a status flag indicating gra compare match or input capture 201 bit 1?nput capture/compare match flag b (imfb): this status flag indicates grb compare match or input capture events. bit 1 imfb description 0 [clearing condition] (initial value) read imfb when imfb = 1, then write 0 in imfb 1 [setting conditions] tcnt = grb when grb functions as a compare match register. tcnt value is transferred to grb by an input capture signal, when grb functions as an input capture register. bit 0?nput capture/compare match flag a (imfa): this status flag indicates gra compare match or input capture events. bit 0 imfa description 0 [clearing condition] (initial value) read imfa when imfa = 1, then write 0 in imfa. dmac activated by imia interrupt (channels 0 to 3 only). 1 [setting conditions] tcnt = gra when gra functions as a compare match register. tcnt value is transferred to gra by an input capture signal, when gra functions as an input capture register. 202 8.2.13 timer interrupt enable register (tier) tier is an 8-bit register. the itu has five tiers, one in each channel. channel abbreviation function 0 tier0 enables or disables interrupt requests. 1 tier1 2 tier2 3 tier3 4 tier4 each tier is an 8-bit readable/writable register that enables and disables overflow interrupt requests and general register compare match and input capture interrupt requests. tier is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?eserved: read-only bits, always read as 1. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 ovie 0 r/w 1 imieb 0 r/w 0 imiea 0 r/w reserved bits overflow interrupt enable enables or disables ovf interrupts input capture/compare match interrupt enable b enables or disables imfb interrupts input capture/compare match interrupt enable a enables or disables imfa interrupts 203 bit 2?verflow interrupt enable (ovie): enables or disables the interrupt requested by the overflow flag (ovf) in tsr when ovf is set to 1. bit 2 ovie description 0 ovi interrupt requested by ovf is disabled (initial value) 1 ovi interrupt requested by ovf is enabled bit 1?nput capture/compare match interrupt enable b (imieb): enables or disables the interrupt requested by the imfb flag in tsr when imfb is set to 1. bit 1 imieb description 0 imib interrupt requested by imfb is disabled (initial value) 1 imib interrupt requested by imfb is enabled bit 0?nput capture/compare match interrupt enable a (imiea): enables or disables the interrupt requested by the imfa flag in tsr when imfa is set to 1. bit 0 imiea description 0 imia interrupt requested by imfa is disabled (initial value) 1 imia interrupt requested by imfa is enabled 204 8.3 cpu interface 8.3.1 16-bit accessible registers the timer counters (tcnts), general registers a and b (gras and grbs), and buffer registers a and b (bras and brbs) are 16-bit registers, and are linked to the cpu by an internal 16-bit data bus. these registers can be written or read a word at a time, or a byte at a time. figures 8-6 and 8-7 show examples of word access to a timer counter (tcnt). figures 8-8, 8-9, 8-10, and 8-11 show examples of byte access to tcnth and tcntl. figure 8-6 access to timer counter (cpu writes to tcnt, word) figure 8-7 access to timer counter (cpu reads tcnt, word) on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl 205 figure 8-8 access to timer counter (cpu writes to tcnt, upper byte) figure 8-9 access to timer counter (cpu writes to tcnt, lower byte) figure 8-10 access to timer counter (cpu reads tcnt, upper byte) on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl 206 figure 8-11 access to timer counter (cpu reads tcnt, lower byte) 8.3.2 8-bit accessible registers the registers other than the timer counters, general registers, and buffer registers are 8-bit registers. these registers are linked to the cpu by an internal 8-bit data bus. figures 8-12 and 8-13 show examples of byte read and write access to a tcr. if a word-size data transfer instruction is executed, two byte transfers are performed. figure 8-12 tcr access (cpu writes to tcr) on-chip data bus cpu h l bus interface h l module data bus tcnth tcntl on-chip data bus cpu h l bus interface h l module data bus tcr 207 figure 8-13 tcr access (cpu reads tcr) on-chip data bus cpu h l bus interface h l module data bus tcr 208 8.4 operation 8.4.1 overview a summary of operations in the various modes is given below. normal operation: each channel has a timer counter and general registers. the timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. general registers a and b can be used for input capture or output compare. synchronous operation: the timer counters in designated channels are preset synchronously. data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. the timer counters can also be cleared synchronously if so designated by the cclr1 and cclr0 bits in the tcrs. pwm mode: a pwm waveform is output from the tioca pin. the output goes to 1 at compare match a and to 0 at compare match b. the duty cycle can be varied from 0% to 100% depending on the settings of gra and grb. when a channel is set to pwm mode, its gra and grb automatically become output compare registers. reset-synchronized pwm mode: channels 3 and 4 are paired for three-phase pwm output with complementary waveforms. (the three phases are related by having a common transition point.) when reset-synchronized pwm mode is selected gra3, grb3, gra4, and grb4 automatically function as output compare registers, tioca3, tiocb3, tioca4, tocxa4, tiocb4, and tocxb4 function as pwm output pins, and tcnt3 operates as an up-counter. tcnt4 operates independently, and is not compared with gra4 or grb4. complementary pwm mode: channels 3 and 4 are paired for three-phase pwm output with non-overlapping complementary waveforms. when complementary pwm mode is selected gra3, grb3, gra4, and grb4 automatically function as output compare registers, and tioca3, tiocb3, tioca4, tocxa4, tiocb4, and tocxb4 function as pwm output pins. tcnt3 and tcnt4 operate as up/down-counters. phase counting mode: the phase relationship between two clock signals input at tclka and tclkb is detected and tcnt2 counts up or down accordingly. when phase counting mode is selected tclka and tclkb become clock input pins and tcnt2 operates as an up/down- counter. 209 buffering if the general register is an output compare register when compare match occurs the buffer register value is transferred to the general register. if the general register is an input capture register when input capture occurs the tcnt value is transferred to the general register, and the previous general register value is transferred to the buffer register. complementary pwm mode the buffer register value is transferred to the general register when tcnt3 and tcnt4 change counting direction. reset-synchronized pwm mode the buffer register value is transferred to the general register at gra3 compare match. 8.4.2 basic functions counter operation: when one of bits str0 to str4 is set to 1 in the timer start register (tstr), the timer counter (tcnt) in the corresponding channel starts counting. the counting can be free-running or periodic. sample setup procedure for counter figure 8-14 shows a sample procedure for setting up a counter. 210 figure 8-14 counter setup procedure (example) 1. set bits tpsc2 to tpsc0 in tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in tcr to select the desired edge(s) of the external clock signal. 2. for periodic counting, set cclr1 and cclr0 in tcr to have tcnt cleared at gra compare match or grb compare match. 3. set tior to select the output compare function of gra or grb, whichever was selected in step 2. 4. write the count period in gra or grb, whichever was selected in step 2. 5. set the str bit to 1 in tstr to start the timer counter. counter setup select counter clock type of counting? periodic counting select counter clear source select output compare register function set period start counter free-running counting start counter periodic counter free-running counter 1 2 3 4 55 211 free-running and periodic counter operation a reset leaves the counters (tcnts) in itu channels 0 to 4 all set as free-running counters. a free-running counter starts counting up when the corresponding bit in tstr is set to 1. when the count overflows from h'ffff to h'0000, the overflow flag (ovf) is set to 1 in the timer status register (tsr). if the corresponding ovie bit is set to 1 in the timer interrupt enable register, a cpu interrupt is requested. after the overflow, the counter continues counting up from h'0000. figure 8-15 illustrates free-running counting. figure 8-15 free-running counter operation when a channel is set to have its counter cleared by compare match, in that channel tcnt operates as a periodic counter. select the output compare function of gra or grb, set bit cclr1 or cclr0 in the timer control register (tcr) to have the counter cleared by compare match, and set the count period in gra or grb. after these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in tstr. when the count matches gra or grb, the imfa or imfb flag is set to 1 in tsr and the counter is cleared to h'0000. if the corresponding imiea or imieb bit is set to 1 in tier, a cpu interrupt is requested at this time. after the compare match, tcnt continues counting up from h'0000. figure 8-16 illustrates periodic counting. tcnt value h'ffff h'0000 str0 to str4 bit ovf time 212 figure 8-16 periodic counter operation count timing internal clock source bits tpsc2 to tpsc0 in tcr select the system clock (? or one of three internal clock sources obtained by prescaling the system clock (?2, ?4, ?8). figure 8-17 shows the timing. figure 8-17 count timing for internal clock sources tcnt value gr h'0000 str bit imf time counter cleared by general register compare match tcnt input tcnt internal clock n ?1 n n + 1 213 external clock source bits tpsc2 to tpsc0 in tcr select an external clock input pin (tclka to tclkd), and its valid edge or edges are selected by bits ckeg1 and ckeg0. the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. shorter pulses will not be counted correctly. figure 8-18 shows the timing when both edges are detected. figure 8-18 count timing for external clock sources (when both edges are detected) tcnt input tcnt external clock input n ?1 n n + 1 214 waveform output by compare match: in itu channels 0, 1, 3, and 4, compare match a or b can cause the output at the tioca or tiocb pin to go to 0, go to 1, or toggle. in channel 2 the output can only go to 0 or go to 1. sample setup procedure for waveform output by compare match figure 8-19 shows a sample procedure for setting up waveform output by compare match. figure 8-19 setup procedure for waveform output by compare match (example) examples of waveform output figure 8-20 shows examples of 0 and 1 output. tcnt operates as a free-running counter, 0 output is selected for compare match a, and 1 output is selected for compare match b. when the pin is already at the selected output level, the pin level does not change. output setup select waveform output mode set output timing start counter waveform output select the compare match output mode (0, 1, or toggle) in tior. when a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (tioca or tiocb). an output compare pin outputs set a value in gra or grb to designate the compare match timing. set the str bit to 1 in tstr to start the timer counter. 1 2 3 0 until the first compare match occurs. 1. 2. 3. 215 figure 8-20 0 and 1 output (examples) figure 8-21 shows examples of toggle output. tcnt operates as a periodic counter, cleared by compare match b. toggle output is selected for both compare match a and b. figure 8-21 toggle output (example) time h'ffff grb tiocb tioca gra no change no change no change no change 1 output 0 output tcnt value grb tiocb tioca gra tcnt value time counter cleared by compare match with grb toggle output toggle output 216 output compare timing the compare match signal is generated in the last state in which tcnt and the general register match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the output compare pin (tioca or tiocb). when tcnt matches a general register, the compare match signal is not generated until the next counter clock pulse. figure 8-22 shows the output compare timing. figure 8-22 output compare timing input capture function: the tcnt value can be captured into a general register when a transition occurs at an input capture/output compare pin (tioca or tiocb). capture can take place on the rising edge, falling edge, or both edges. the input capture function can be used to measure pulse width or period. sample setup procedure for input capture figure 8-23 shows a sample procedure for setting up input capture. n + 1 n n tcnt input clock tcnt gr compare match signal tioca, tiocb 217 figure 8-23 setup procedure for input capture (example) examples of input capture figure 8-24 illustrates input capture when the falling edge of tiocb and both edges of tioca are selected as capture edges. tcnt is cleared by input capture into grb. figure 8-24 input capture (example) input selection select input-capture input start counter input capture set tior to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. clear the port data direction bit to 0 before making these tior settings. set the str bit to 1 in tstr to start the timer counter. 1 2 1. 2. h'0005 h'0180 time h'0180 h'0160 h'0005 h'0000 tiocb tioca gra grb counter cleared by tiocb input (falling edge) tcnt value h'0160 218 input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected by settings in tior. figure 8-25 shows the timing when the rising edge is selected. the pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. figure 8-25 input capture signal timing n n input-capture input internal input capture signal tcnt gra, grb 219 8.4.3 synchronization the synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). with appropriate tcr settings, two or more timer counters can also be cleared simultaneously (synchronous clear). synchronization enables additional general registers to be associated with a single time base. synchronization can be selected for all channels (0 to 4). sample setup procedure for synchronization: figure 8-26 shows a sample procedure for setting up synchronization. figure 8-26 setup procedure for synchronization (example) setup for synchronization synchronous preset set the sync bits to 1 in tsnc for the channels to be synchronized. when a value is written in tcnt in one of the synchronized channels, the same value is simultaneously written in tcnt in the other channels (synchronized preset). 1. 2. 2 3 1 5 4 5 select synchronization synchronous preset write to tcnt synchronous clear clearing synchronized to this channel? select counter clear source start counter counter clear synchronous clear start counter select counter clear source yes no set the cclr1 or cclr0 bit in tcr to have the counter cleared by compare match or input capture. set the cclr1 and cclr0 bits in tcr to have the counter cleared synchronously. set the str bits in tstr to 1 to start the synchronized counters. 3. 4. 5. 220 example of synchronization: figure 8-27 shows an example of synchronization. channels 0, 1, and 2 are synchronized, and are set to operate in pwm mode. channel 0 is set for counter clearing by compare match with grb0. channels 1 and 2 are set for synchronous counter clearing. the timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with grb0. a three-phase pwm waveform is output from pins tioca0, tioca1, and tioca2. for further information on pwm mode, see section 8.4.4, pwm mode. figure 8-27 synchronization (example) tioca2 time tioca1 tioca0 gra2 gra1 grb2 gra0 grb1 grb0 value of tcnt0 to tcnt2 cleared by compare match with grb0 221 8.4.4 pwm mode in pwm mode gra and grb are paired and a pwm waveform is output from the tioca pin. gra specifies the time at which the pwm output changes to 1. grb specifies the time at which the pwm output changes to 0. if either gra or grb is selected as the counter clear source, a pwm waveform with a duty cycle from 0% to 100% is output at the tioca pin. pwm mode can be selected in all channels (0 to 4). table 8-4 summarizes the pwm output pins and corresponding registers. if the same value is set in gra and grb, the output does not change when compare match occurs. table 8-4 pwm output pins and registers channel output pin 1 output 0 output 0 tioca0 gra0 grb0 1 tioca1 gra1 grb1 2 tioca2 gra2 grb2 3 tioca3 gra3 grb3 4 tioca4 gra4 grb4 222 sample setup procedure for pwm mode: figure 8-28 shows a sample procedure for setting up pwm mode. figure 8-28 setup procedure for pwm mode (example) pwm mode 1. set bits tpsc2 to tpsc0 in tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in tcr to select the desired edge(s) of the external clock signal. pwm mode select counter clock 1 select counter clear source 2 set gra 3 set grb 4 select pwm mode 5 start counter 6 2. set bits cclr1 and cclr0 in tcr to select the counter clear source. 3. set the time at which the pwm waveform should go to 1 in gra. 4. set the time at which the pwm waveform should go to 0 in grb. 5. set the pwm bit in tmdr to select pwm mode. when pwm mode is selected, regardless of the tior contents, gra and grb become output compare registers specifying the times at which the pwm goes to 1 and 0. the tioca pin automatically becomes the pwm output pin. the tiocb pin conforms to the settings of bits iob1 and iob0 in tior. if tiocb output is not desired, clear both iob1 and iob0 to 0. 6. set the str bit to 1 in tstr to start the timer counter. 223 examples of pwm mode: figure 8-29 shows examples of operation in pwm mode. the pwm waveform is output from the tioca pin. the output goes to 1 at compare match with gra, and to 0 at compare match with grb. in the examples shown, tcnt is cleared by compare match with gra or grb. synchronized operation and free-running counting are also possible. figure 8-29 pwm mode (example 1) tcnt value counter cleared by compare match with gra time gra grb tioca a. counter cleared by gra tcnt value counter cleared by compare match with grb time grb gra tioca b. counter cleared by grb h'0000 h'0000 224 figure 8-30 shows examples of the output of pwm waveforms with duty cycles of 0% and 100%. if the counter is cleared by compare match with grb, and gra is set to a higher value than grb, the duty cycle is 0%. if the counter is cleared by compare match with gra, and grb is set to a higher value than gra, the duty cycle is 100%. figure 8-30 pwm mode (example 2) tcnt value counter cleared by compare match with grb time grb gra tioca a. 0% duty cycle tcnt value counter cleared by compare match with gra time gra grb tioca b. 100% duty cycle write to gra write to gra write to grb write to grb h'0000 h'0000 225 8.4.5 reset-synchronized pwm mode in reset-synchronized pwm mode channels 3 and 4 are combined to produce three pairs of complementary pwm waveforms, all having one waveform transition point in common. when reset-synchronized pwm mode is selected tioca3, tiocb3, tioca4, tocxa4, tiocb4, and tocxb4 automatically become pwm output pins, and tcnt3 functions as an up- counter. table 8-5 lists the pwm output pins. table 8-6 summarizes the register settings. table 8-5 output pins in reset-synchronized pwm mode channel output pin description 3 tioca3 pwm output 1 tiocb3 pwm output 1 (complementary waveform to pwm output 1) 4 tioca4 pwm output 2 tocxa4 pwm output 2 (complementary waveform to pwm output 2) tiocb4 pwm output 3 tocxb4 pwm output 3 (complementary waveform to pwm output 3) table 8-6 register settings in reset-synchronized pwm mode register setting tcnt3 initially set to h'0000 tcnt4 not used (operates independently) gra3 specifies the count period of tcnt3 grb3 specifies a transition point of pwm waveforms output from tioca3 and tiocb3 gra4 specifies a transition point of pwm waveforms output from tioca4 and tocxa4 grb4 specifies a transition point of pwm waveforms output from tiocb4 and tocxb4 226 sample setup procedure for reset-synchronized pwm mode: figure 8-31 shows a sample procedure for setting up reset-synchronized pwm mode. figure 8-31 setup procedure for reset-synchronized pwm mode (example) reset-synchronized pwm mode 1. clear the str3 bit in tstr to 0 to halt tcnt3. reset-synchronized pwm mode must be set up while tcnt3 is halted. reset-synchronized pwm mode stop counter 1 select counter clock 2 select counter clear source 3 select reset-synchronized pwm mode 4 set tcnt 5 set general registers 6 2. set bits tpsc2 to tpsc0 in tcr to select the counter clock source for channel 3. if an external clock source is selected, select the external clock edge(s) with bits ckeg1 and ckeg0 in tcr. 3. set bits cclr1 and cclr0 in tcr3 to select gra3 compare match as the counter clear source. 4. set bits cmd1 and cmd0 in tfcr to select reset-synchronized pwm mode. tioca3, tiocb3, tioca4, tiocb4, tocxa4, and tocxb4 automatically become pwm output pins. 5. preset tcnt3 to h'0000. tcnt4 need not be preset. start counter 7 6. gra3 is the waveform period register. set the waveform period value in gra3. set transition times of the pwm output waveforms in grb3, gra4, and grb4. set times within the compare match range of tcnt3. x gra3 (x: setting value) 7. set the str3 bit in tstr to 1 to start tcnt3. 227 example of reset-synchronized pwm mode: figure 8-32 shows an example of operation in reset-synchronized pwm mode. tcnt3 operates as an up-counter in this mode. tcnt4 operates independently, detached from gra4 and grb4. when tcnt3 matches gra3, tcnt3 is cleared and resumes counting from h'0000. the pwm outputs toggle at compare match with grb3, gra4, grb4, and tcnt3 respectively, and all toggle when the counter is cleared. figure 8-32 operation in reset-synchronized pwm mode (example) (when ols3 = ols4 = 1) for the settings and operation when reset-synchronized pwm mode and buffer mode are both selected, see section 8.4.8, buffering. tcnt3 value counter cleared at compare match with gra3 time gra3 grb3 gra4 grb4 h'0000 tioca 3 tiocb 3 tioca 4 tocxa 4 tiocb 4 tocxb 4 228 8.4.6 complementary pwm mode in complementary pwm mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping pwm waveforms. when complementary pwm mode is selected tioca 3 , tiocb 3 , tioca 4 , tocxa 4 , tiocb 4 , and tocxb 4 automatically become pwm output pins, and tcnt3 and tcnt4 function as up/down-counters. table 8-7 lists the pwm output pins. table 8-8 summarizes the register settings. table 8-7 output pins in complementary pwm mode channel output pin description 3 tioca 3 pwm output 1 tiocb 3 pwm output 1 (non-overlapping complementary waveform to pwm output 1) 4 tioca 4 pwm output 2 tocxa 4 pwm output 2 (non-overlapping complementary waveform to pwm output 2) tiocb 4 pwm output 3 tocxb 4 pwm output 3 (non-overlapping complementary waveform to pwm output 3) table 8-8 register settings in complementary pwm mode register setting tcnt3 initially specifies the non-overlap margin (difference to tcnt4) tcnt4 initially set to h'0000 gra3 specifies the upper limit value of tcnt3 minus 1 grb3 specifies a transition point of pwm waveforms output from tioca 3 and tiocb 3 gra4 specifies a transition point of pwm waveforms output from tioca 4 and tocxa 4 grb4 specifies a transition point of pwm waveforms output from tiocb 4 and tocxb 4 229 setup procedure for complementary pwm mode: figure 8-33 shows a sample procedure for setting up complementary pwm mode. figure 8-33 setup procedure for complementary pwm mode (example) complementary pwm mode 1. clear bits str3 and str4 to 0 in tstr to halt the timer counters. complementary pwm mode must be set up while tcnt3 and tcnt4 are halted. complementary pwm mode stop counting 1 select counter clock 2 select complementary pwm mode 3 set tcnts 4 set general registers 5 start counters 6 2. set bits tpsc2 to tpsc0 in tcr to select the same counter clock source for channels 3 and 4. if an external clock source is selected, select the external clock edge(s) with bits ckeg1 and ckeg0 in tcr. do not select any counter clear source with bits cclr1 and cclr0 in tcr. 3. set bits cmd1 and cmd0 in tfcr to select complementary pwm mode. tioca 3 , tiocb 3 , tioca 4 , tiocb 4 , tocxa 4 , and tocxb 4 automatically become pwm output pins. 4. clear tcnt4 to h'0000. set the non-overlap margin in tcnt3. do not set tcnt3 and tcnt4 to the same value. 5. gra3 is the waveform period register. set the upper limit value of tcnt3 minus 1 in gra3. set transition times of the pwm output waveforms in grb3, gra4, and grb4. set times within the compare match range of tcnt3 and tcnt4. t x (x: initial setting of grb3, gra4, or grb4. t: initial setting of tcnt3) 6. set bits str3 and str4 in tstr to 1 to start tcnt3 and tcnt4. note: after exiting complementary pwm mode, to resume operating in complementary pwm mode, follow the entire setup procedure from step 1 again. 230 clearing complementary pwm mode: figure 8-34 shows a sample procedure for clearing complementary pwm mode. figure 8-34 clearing procedure for complementary pwm mode (example) 231 complementary pwm mode normal operation clear complementary mode 1 stop counting 2 1. 2. clear bit cmd1 in tfcr to 0, and set channels 3 and 4 to normal operating mode. after setting channels 3 and 4 to normal operating mode, wait at least one clock count before clearing bits str3 and str4 of tstr to 0 to stop the counter operation of tcnt3 and tcnt4. examples of complementary pwm mode: figure 8-35 shows an example of operation in complementary pwm mode. tcnt3 and tcnt4 operate as up/down-counters, counting down from compare match between tcnt3 and gra3 and counting up from the point at which tcnt4 underflows. during each up-and-down counting cycle, pwm waveforms are generated by compare match with general registers grb3, gra4, and grb4. since tcnt3 is initially set to a higher value than tcnt4, compare match events occur in the sequence tcnt3, tcnt4, tcnt4, tcnt3. figure 8-35 operation in complementary pwm mode (example 1) (when ols3 = ols4 = 1) tcnt3 and tcnt4 values down-counting starts at compare match between tcnt3 and gra3 time gra3 grb3 gra4 grb4 h'0000 tioca3 tiocb3 tioca4 tocxa4 tiocb4 tocxb4 tcnt3 tcnt4 up-counting starts when tcnt4 underflows 232 figure 8-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary pwm mode. in this example the outputs change at compare match with grb3, so waveforms with duty cycles of 0% or 100% can be output by setting grb3 to a value larger than gra3. the duty cycle can be changed easily during operation by use of the buffer registers. for further information see section 8.4.8, buffering. figure 8-36 operation in complementary pwm mode (example 2) (when ols3 = ols4 = 1) tcnt3 and tcnt4 values time gra3 grb3 tioca3 tiocb3 0% duty cycle a. 0% duty cycle tcnt3 and tcnt4 values time gra3 grb3 tioca3 tiocb3 100% duty cycle b. 100% duty cycle h'0000 h'0000 233 in complementary pwm mode, tcnt3 and tcnt4 overshoot and undershoot at the transitions between up-counting and down-counting. the setting conditions for the imfa bit in channel 3 and the ovf bit in channel 4 differ from the usual conditions. in buffered operation the buffer transfer conditions also differ. timing diagrams are shown in figures 8-37 and 8-38. figure 8-37 overshoot timing tcnt3 gra3 imfa buffer transfer signal (br to gr) gr n ?1 n n + 1 n n ?1 n set to 1 flag not set no buffer transfer buffer transfer 234 figure 8-38 undershoot timing in channel 3, imfa is set to 1 only during up-counting. in channel 4, ovf is set to 1 only when an underflow occurs. when buffering is selected, buffer register contents are transferred to the general register at compare match a3 during up-counting, and when tcnt4 underflows. general register settings in complementary pwm mode: when setting up general registers for complementary pwm mode or changing their settings during operation, note the following points. initial settings do not set values from h'0000 to t ?1 (where t is the initial value of tcnt3). after the counters start and the first compare match a3 event has occurred, however, settings in this range also become possible. changing settings use the buffer registers. correct waveform output may not be obtained if a general register is written to directly. cautions on changes of general register settings figure 8-39 shows six correct examples and one incorrect example. tcnt4 ovf buffer transfer signal (br to gr) gr h'0001 h'0000 h'ffff h'0000 set to 1 flag not set no buffer transfer buffer transfer underflow overflow 235 figure 8-39 changing a general register setting by buffer transfer (example 1) buffer transfer at transition from up-counting to down-counting if the general register value is in the range from gra3 ?t + 1 to gra3, do not transfer a buffer register value outside this range. conversely, if the general register value is outside this range, do not transfer a value within this range. see figure 8-40. figure 8-40 changing a general register setting by buffer transfer (caution 1) gra3 gr h'0000 br gr not allowed gra3 + 1 gra3 gra3 ?t + 1 gra3 ?t illegal changes tcnt3 tcnt4 236 buffer transfer at transition from down-counting to up-counting if the general register value is in the range from h'0000 to t ?1, do not transfer a buffer register value outside this range. conversely, when a general register value is outside this range, do not transfer a value within this range. see figure 8-41. figure 8-41 changing a general register setting by buffer transfer (caution 2) t t ?1 h'0000 h'ffff illegal changes tcnt3 tcnt4 237 general register settings outside the counting range (h'0000 to gra3) waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. when a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times. see figure 8-42. figure 8-42 changing a general register setting by buffer transfer (example 2) settings can be made in this way by detecting gra3 compare match or tcnt4 underflow before writing to the buffer register. 0% duty cycle 100% duty cycle write during down-counting write during up-counting gra3 gr h'0000 output pin output pin br gr 238 8.4.7 phase counting mode in phase counting mode the phase difference between two external clock inputs (at the tclka and tclkb pins) is detected, and tcnt2 counts up or down accordingly. in phase counting mode, the tclka and tclkb pins automatically function as external clock input pins and tcnt2 becomes an up/down-counter, regardless of the settings of bits tpsc2 to tpsc0, ckeg1, and ckeg0 in tcr2. settings of bits cclr1, cclr0 in tcr2, and settings in tior2, tier2, tsr2, gra2, and grb2 are valid. the input capture and output compare functions can be used, and interrupts can be generated. phase counting is available only in channel 2. sample setup procedure for phase counting mode: figure 8-43 shows a sample procedure for setting up phase counting mode. figure 8-43 setup procedure for phase counting mode (example) phase counting mode select phase counting mode select flag setting condition start counter 1 2 3 phase counting mode 1. 2. 3. set the mdf bit in tmdr to 1 to select phase counting mode. select the flag setting condition with the fdir bit in tmdr. set the str2 bit to 1 in tstr to start the timer counter. 239 example of phase counting mode: figure 8-44 shows an example of operations in phase counting mode. table 8-9 lists the up-counting and down-counting conditions for tcnt2. in phase counting mode both the rising and falling edges of tclka and tclkb are counted. the phase difference between tclka and tclkb must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. see figure 8-45. figure 8-44 operation in phase counting mode (example) table 8-9 up/down counting conditions counting direction up-counting down-counting tclkb high low high low tclka low high low high figure 8-45 phase difference, overlap, and pulse width in phase counting mode tcnt2 value counting up counting down time tclkb tclka tclka tclkb phase difference phase difference pulse width pulse width overlap overlap phase difference and overlap: pulse width: at least 1.5 states at least 2.5 states 240 8.4.8 buffering buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized pwm mode and complementary pwm mode. buffering is available only in channels 3 and 4. buffering operations under the conditions mentioned above are described next. general register used for output compare the buffer register value is transferred to the general register at compare match. see figure 8-46. figure 8-46 compare match buffering general register used for input capture the tcnt value is transferred to the general register at input capture. the previous general register value is transferred to the buffer register. see figure 8-47. figure 8-47 input capture buffering compare match signal comparator tcnt gr br input capture signal br gr tcnt 241 complementary pwm mode the buffer register value is transferred to the general register when tcnt3 and tcnt4 change counting direction. this occurs at the following two times: when tcnt3 matches gra3 when tcnt4 underflows reset-synchronized pwm mode the buffer register value is transferred to the general register at compare match a3. sample buffering setup procedure: figure 8-48 shows a sample buffering setup procedure. figure 8-48 buffering setup procedure (example) buffering select general register functions set buffer bits start counters buffered operation 11. 2. 3. 2 3 set tior to select the output compare or input capture function of the general registers. set bits bfa3, bfa4, bfb3, and bfb4 in tfcr to select buffering of the required general registers. set the str bits to 1 in tstr to start the timer counters. 242 examples of buffering: figure 8-49 shows an example in which gra is set to function as an output compare register buffered by bra, tcnt is set to operate as a periodic counter cleared by grb compare match, and tioca and tiocb are set to toggle at compare match a and b. because of the buffer setting, when tioca toggles at compare match a, the bra value is simultaneously transferred to gra. this operation is repeated each time compare match a occurs. figure 8-50 shows the transfer timing. figure 8-49 register buffering (example 1: buffering of output compare register) grb h'0250 h'0200 h'0100 h'0000 bra gra tiocb tioca tcnt value counter cleared by compare match b time toggle output toggle output compare match a h'0200 h'0250 h'0100 h'0200 h'0100 h'0200 h'0200 243 figure 8-50 compare match and buffer transfer timing (example) tcnt br gr compare match signal buffer transfer signal n n + 1 nn n 244 figure 8-51 shows an example in which gra is set to function as an input capture register buffered by bra, and tcnt is cleared by input capture b. the falling edge is selected as the input capture edge at tiocb. both edges are selected as input capture edges at tioca. because of the buffer setting, when the tcnt value is captured into gra at input capture a, the previous gra value is simultaneously transferred to bra. figure 8-52 shows the transfer timing. figure 8-51 register buffering (example 2: buffering of input capture register) h'0180 h'0160 h'0005 h'0000 tiocb toica gra bra grb h'0005 h'0160 h'0005 h'0180 tcnt value counter cleared by input capture b time input capture a h'0160 245 figure 8-52 input capture and buffer transfer timing (example) tcnt gr br tioc pin input capture signal n n + 1 n n m n + 1 n n m m n m 246 figure 8-53 shows an example in which grb3 is buffered by brb3 in complementary pwm mode. buffering is used to set grb3 to a higher value than gra3, generating a pwm waveform with 0% duty cycle. the brb3 value is transferred to grb3 when tcnt3 matches gra3, and when tcnt4 underflows. figure 8-53 register buffering (example 4: buffering in complementary pwm mode) tcnt3 and tcnt4 values time gra3 h'0999 h'0000 tcnt3 tcnt4 grb3 h'1fff brb3 grb3 tioca3 tiocb3 h'0999 h'0999 h'0999 h'1fff h'0999 h'1fff h'1fff h'0999 247 8.4.9 itu output timing the itu outputs from channels 3 and 4 can be disabled by bit settings in toer or by an external trigger, or inverted by bit settings in tocr. timing of enabling and disabling of itu output by toer: in this example an itu output is disabled by clearing a master enable bit to 0 in toer. an arbitrary value can be output by appropriate settings of the data register (dr) and data direction register (ddr) of the corresponding input/output port. figure 8-54 illustrates the timing of the enabling and disabling of itu output by toer. figure 8-54 timing of disabling of itu output by writing to toer (example) address toer itu output pin toer address timer output i/o port generic input/output itu output t 1 t 2 t 3 248 timing of disabling of itu output by external trigger: if the xtgd bit is cleared to 0 in tocr in reset-synchronized pwm mode or complementary pwm mode, when an input capture a signal occurs in channel 1, the master enable bits are cleared to 0 in toer, disabling itu output. figure 8-55 shows the timing. figure 8-55 timing of disabling of itu output by external trigger (example) timing of output inversion by tocr: the output levels in reset-synchronized pwm mode and complementary pwm mode can be inverted by inverting the output level select bits (ols4 and ols3) in tocr. figure 8-56 shows the timing. figure 8-56 timing of inverting of itu output level by writing to tocr (example) tioca1 pin toer itu output i/o port itu output i/o port generic input/output generic input/output itu output itu output input capture signal itu output pins nn h'c0 h'c0 n: arbitrary setting (h'c1 to h'ff) address tocr itu output pin tocr address inverted t 1 t 2 t 3 249 8.5 interrupts the itu has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 setting of status flags timing of setting of imfa and imfb at compare match: imfa and imfb are set to 1 by a compare match signal generated when tcnt matches a general register (gr). the compare match signal is generated in the last state in which the values match (when tcnt is updated from the matching count to the next count). therefore, when tcnt matches a general register, the compare match signal is not generated until the next timer clock input. figure 8-57 shows the timing of the setting of imfa and imfb. figure 8-57 timing of setting of imfa and imfb by compare match tcnt gr imf imi tcnt input clock compare match signal n n + 1 n 250 timing of setting of imfa and imfb by input capture: imfa and imfb are set to 1 by an input capture signal. the tcnt contents are simultaneously transferred to the corresponding general register. figure 8-58 shows the timing. figure 8-58 timing of setting of imfa and imfb by input capture timing of setting of overflow flag (ovf): ovf is set to 1 when tcnt overflows from h'ffff to h'0000 or underflows from h'0000 to h'ffff. figure 8-59 shows the timing. input capture signal n n imf tcnt gr imi 251 figure 8-59 timing of setting of ovf 8.5.2 clearing of status flags if the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 8-60 shows the timing. figure 8-60 timing of clearing of status flags overflow signal h'ffff h'0000 tcnt ovf ovi ? address imf, ovf tsr write cycle tsr address t 1 t 2 t 3 252 8.5.3 interrupt sources each itu channel can generate a compare match/input capture a interrupt, a compare match/input capture b interrupt, and an overflow interrupt. in total there are 15 interrupt sources, all independently vectored. an interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1. the priority order of the channels can be modified in interrupt priority registers a and b (ipra and iprb). for details see section 5, interrupt controller. table 8-10 lists the interrupt sources. table 8-10 itu interrupt sources interrupt channel source description priority * 0 imia0 compare match/input capture a0 high imib0 compare match/input capture b0 ovi0 overflow 0 1 imia1 compare match/input capture a1 imib1 compare match/input capture b1 ovi1 overflow 1 2 imia2 compare match/input capture a2 imib2 compare match/input capture b2 ovi2 overflow 2 3 imia3 compare match/input capture a3 imib3 compare match/input capture b3 ovi3 overflow 3 4 imia4 compare match/input capture a4 imib4 compare match/input capture b4 ovi4 overflow 4 low note: * the priority immediately after a reset is indicated. inter-channel priorities can be changed by settings in ipra and iprb. 253 8.6 usage notes this section describes contention and other matters requiring special attention during itu operations. contention between tcnt write and clear: if a counter clear signal occurs in the t 3 state of a tcnt write cycle, clearing of the counter takes priority and the write is not performed. see figure 8-61. figure 8-61 contention between tcnt write and clear address internal write signal counter clear signal tcnt tcnt write cycle tcnt address n h'0000 t 1 t 2 t 3 254 contention between tcnt word write and increment: if an increment pulse occurs in the t 3 state of a tcnt word write cycle, writing takes priority and tcnt is not incremented. see figure 8-62. figure 8-62 contention between tcnt word write and increment ? address internal write signal tcnt input clock tcnt n tcnt address m tcnt write data tcnt word write cycle t 1 t 2 t 3 255 contention between tcnt byte write and increment: if an increment pulse occurs in the t 2 or t 3 state of a tcnt byte write cycle, writing takes priority and tcnt is not incremented. the tcnt byte that was not written retains its previous value. see figure 8-63, which shows an increment pulse occurring in the t 2 state of a byte write to tcnth. figure 8-63 contention between tcnt byte write and increment ? address internal write signal tcnt input clock tcnth tcntl tcnth byte write cycle t 1 t 2 t 3 n tcnth address m tcnth write data xx x + 1 256 contention between general register write and compare match: if a compare match occurs in the t 3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. see figure 8-64. figure 8-64 contention between general register write and compare match ? address internal write signal tcnt gr compare match signal general register write cycle t 1 t 2 t 3 n gr address m n n + 1 general register write data inhibited 257 contention between tcnt write and overflow or underflow: if an overflow occurs in the t 3 state of a tcnt write cycle, writing takes priority and the counter is not incremented. ovf is set to 1.the same holds for underflow. see figure 8-65. figure 8-65 contention between tcnt write and overflow ? address internal write signal tcnt input clock overflow signal tcnt ovf h'ffff tcnt address m tcnt write data tcnt write cycle t 1 t 2 t 3 258 contention between general register read and input capture: if an input capture signal occurs during the t 3 state of a general register read cycle, the value before input capture is read. see figure 8-66. figure 8-66 contention between general register read and input capture ? address internal read signal input capture signal gr internal data bus gr address x general register read cycle t 1 t 2 t 3 xm 259 contention between counter clearing by input capture and counter increment: if an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. the counter is not incremented by the increment signal. the value before the counter is cleared is transferred to the general register. see figure 8-67. figure 8-67 contention between counter clearing by input capture and counter increment input capture signal counter clear signal tcnt input clock tcnt gr n n h'0000 260 contention between general register write and input capture: if an input capture signal occurs in the t 3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. see figure 8-68. figure 8-68 contention between general register write and input capture note on waveform period setting: when a counter is cleared by compare match, the counter is cleared in the last state at which the tcnt value matches the general register value, at the time when this value would normally be updated to the next count. the actual counter frequency is therefore given by the following formula: f = (f: counter frequency. ? system clock frequency. n: value set in general register.) ? address internal write signal input capture signal tcnt gr m gr address general register write cycle t 1 t 2 t 3 m (n + 1) 261 contention between buffer register write and input capture: if a buffer register is used for input capture buffering and an input capture signal occurs in the t 3 state of a write cycle, input capture takes priority and the write to the buffer register is not performed. see figure 8-69. figure 8-69 contention between buffer register write and input capture ? address internal write signal input capture signal gr br br address buffer register write cycle t 1 t 2 t 3 nx mn tcnt value 262 note on synchronous preset: when channels are synchronized, if a tcnt value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (example) when channels 2 and 3 are synchronized note on setup of reset-synchronized pwm mode and complementary pwm mode: when setting bits cmd1 and cmd0 in tfcr, take the following precautions: write to bits cmd1 and cmd0 only when tcnt3 and tcnt4 are stopped. do not switch directly between reset-synchronized pwm mode and complementary pwm mode. first switch to normal mode (by clearing bit cmd1 to 0), then select reset- synchronized pwm mode or complementary pwm mode. ? byte write to channel 2 or byte write to channel 3 tcnt2 tcnt3 w y x z tcnt2 tcnt3 a a x x tcnt2 tcnt3 y y a a tcnt2 tcnt3 w y x z tcnt2 tcnt3 a a b b ? word write to channel 2 or word write to channel 3 upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte write a to upper byte of channel 2 write a to lower byte of channel 3 write ab word to channel 2 or 3 263 itu operating modes table 8-11 (a) itu operating modes (channel 0) register settings tsnc tmdr tfcr tocr toer tior0 tcr0 reset- comple- synchro- output synchro- mentary nized buffer- level master clear clock operating mode nization mdf fdir pwm pwm pwm ing xtgd select enable ioa iob select select synchronous preset sync0 = 1 o oooo pwm mode o pwm0 = 1 * o * oo output compare a o pwm0 = 0 ioa2 = 0 ooo other bits unrestricted output compare b o o o iob2 = 0 oo other bits unrestricted input capture a o pwm0 = 0 ioa2 = 1 ooo other bits unrestricted input capture b o pwm0 = 0 o iob2 = 1 oo other bits unrestricted counter by compare o o oo cclr1 = 0 o clearing match/input cclr0 = 1 capture a by compare o o oo cclr1 = 1 o match/input cclr0 = 0 capture b syn- sync0 = 1 o oo cclr1 = 1 o chronous cclr0 = 1 clear legend: o setting available (valid). setting does not affect this mode. note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 264 table 8-11 (b) itu operating modes (channel 1) register settings tsnc tmdr tfcr tocr toer tior1 tcr1 reset- comple- synchro- output synchro- mentary nized buffer- level master clear clock operating mode nization mdf fdir pwm pwm pwm ing xtgd select enable ioa iob select select synchronous preset sync1 = 1 o oooo pwm mode o pwm1 = 1 o * 1 oo output compare a o pwm1 = 0 ioa2 = 0 ooo other bits unrestricted output compare b o o o iob2 = 0 oo other bits unrestricted input capture a o pwm1 = 0 o * 2 ioa2 = 1 ooo other bits unrestricted input capture b o pwm1 = 0 o iob2 = 1 oo other bits unrestricted counter by compare o o oo cclr1 = 0 o clearing match/input cclr0 = 1 capture a by compare o o oo cclr1 = 1 o match/input cclr0 = 0 capture b syn- sync1 = 1 o oo cclr1 = 1 o chronous cclr0 = 1 clear legend: o setting available (valid). setting does not affect this mode. notes: 1. the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 2. valid only when channels 3 and 4 are operating in complementary pwm mode or reset-synchronized pwm mode. 265 table 8-11 (c) itu operating modes (channel 2) register settings tsnc tmdr tfcr tocr toer tior2 tcr2 reset- comple- synchro- output synchro- mentary nized buffer- level master clear clock operating mode nization mdf fdir pwm pwm pwm ing xtgd select enable ioa iob select select synchronous preset sync2 = 1 o o oooo pwm mode oo pwm2 = 1 o * oo output compare a oo pwm2 = 0 ioa2 = 0 ooo other bits unrestricted output compare b oo o o iob2 = 0 oo other bits unrestricted input capture a o pwm2 = 0 ioa2 = 1 ooo other bits unrestricted input capture b o pwm2 = 0 o iob2 = 1 oo other bits unrestricted counter by compare oo o oo cclr1 = 0 o clearing match/input cclr0 = 1 capture a by compare oo o oo cclr1 = 1 o match/input cclr0 = 0 capture b syn- sync2 = 1 o o oo cclr1 = 1 o chronous cclr0 = 1 clear phase counting o mdf = 1 oo ooo mode legend: o setting available (valid). setting does not affect this mode. note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 266 table 8-11 (d) itu operating modes (channel 3) register settings tsnc tmdr tfcr tocr toer tior3 tcr3 comple- reset- output synchro- mentary synchro- level master clear clock operating mode nization mdf fdir pwm pwm nized pwm buffering xtgd select enable ioa iob select select synchronous preset sync3 = 1 oo * 3 oo o * 1 oooo pwm mode o pwm3 = 1 cmd1 = 0 cmd1 = 0 o o o * 2 oo output compare a o pwm3 = 0 cmd1 = 0 cmd1 = 0 o o ioa2 = 0 oo o other bits unrestricted output compare b o o cmd1 = 0 cmd1 = 0 o oo iob2 = 0 oo other bits unrestricted input capture a o pwm3 = 0 cmd1 = 0 cmd1 = 0 o ea3 ignored ioa2 = 1 oo o other bits other bits unrestricted unrestricted input capture b o pwm3 = 0 cmd1 = 0 cmd1 = 0 o ea3 ignored o ioa2 = 1 oo other bits other bits unrestricted unrestricted counter by compare o o illegal setting: o * 4 o o * 1 oo cclr1 = 0 o clearing match/input cmd1 = 1 cclr0 = 1 capture a cmd0 = 0 by compare o o cmd1 = 0 cmd1 = 0 o o * 1 oo cclr1 = 1 o match/input cclr0 = 0 capture b syn- sync3 = 1 o illegal setting: oo o * 1 oo cclr1 = 1 o chronous cmd1 = 1 cclr0 = 1 clear cmd0 = 0 complementary o * 3 cmd1 = 1 cmd1 = 1 oo * 6 oo cclr1 = 0 o * 5 pwm mode cmd0 = 0 cmd0 = 0 cclr0 = 0 reset-synchronized o cmd1 = 1 cmd1 = 1 oo * 6 oo cclr1 = 0 o pwm mode cmd0 = 1 cmd0 = 1 cclr0 = 1 buffering o oo o bfa3 = 1 o * 1 oooo (bra) other bits unrestricted buffering o oo o bfb3 = 1 o * 1 oooo (brb) other bits unrestricted legend: o setting available (valid). setting does not affect this mode. notes: 1. master enable bit settings are valid only during waveform output. 2. the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 3. do not set both channels 3 and 4 for synchronous operation when complementary pwm mode is selected. 4. the counter cannot be cleared by input capture a when reset-synchronized pwm mode is selected. 5. in complementary pwm mode, select the same clock source for channels 3 and 4. 6. use the input capture a function in channel 1. 267 table 8-11 (e) itu operating modes (channel 4) register settings tsnc tmdr tfcr tocr toer tior4 tcr4 comple- reset- output synchro- mentary synchro- level master clear clock operating mode nization mdf fdir pwm pwm nized pwm buffering xtgd select enable ioa iob select select synchronous preset sync4 = 1 oo * 3 oo o * 1 oooo pwm mode o pwm4 = 1 cmd1 = 0 cmd1 = 0 o o o * 2 oo output compare a o pwm4 = 0 cmd1 = 0 cmd1 = 0 o o ioa2 = 0 oo o other bits unrestricted output compare b o o cmd1 = 0 cmd1 = 0 o oo iob2 = 0 oo other bits unrestricted input capture a o pwm4 = 0 cmd1 = 0 cmd1 = 0 o ea4 ignored ioa2 = 1 oo o other bits other bits unrestricted unrestricted input capture b o pwm4 = 0 cmd1 = 0 cmd1 = 0 o eb4 ignored o iob2 = 1 oo other bits other bits unrestricted unrestricted counter by compare o o illegal setting: o * 4 o o * 1 oo cclr1 = 0 o clearing match/input cmd1 = 1 cclr0 = 1 capture a cmd0 = 0 by compare o o illegal setting: o * 4 o o * 1 oo cclr1 = 1 o match/input cmd1 = 1 cclr0 = 0 capture b cmd0 = 0 syn- sync4 = 1 o illegal setting: o * 4 o o * 1 oo cclr1 = 1 o chronous cmd1 = 1 cclr0 = 1 clear cmd0 = 0 complementary o * 3 cmd1 = 1 cmd1 = 1 oooo cclr1 = 0 o * 5 pwm mode cmd0 = 0 cmd0 = 0 cclr0 = 0 reset-synchronized o cmd1 = 1 cmd1 = 1 oooo o * 6 o * 6 pwm mode cmd0 = 1 cmd0 = 1 buffering o oo o bfa4 = 1 o * 1 oooo (bra) other bits unrestricted buffering o oo o bfb4 = 1 o * 1 oooo (brb) other bits unrestricted legend: o setting available (valid). setting does not affect this mode. notes: 1. master enable bit settings are valid only during waveform output. 2. the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 3. do not set both channels 3 and 4 for synchronous operation when complementary pwm mode is selected. 4. when reset-synchronized pwm mode is selected, tcnt4 operates independently and the counter clearing function is available. waveform output is not affected. 5. in complementary pwm mode, select the same clock source for channels 3 and 4. 6. tcr4 settings are valid in reset-synchronized pwm mode, but tcnt4 operates independently, without affecting waveform output. 268 section 9 programmable timing pattern controller 9.1 overview the h8/3032 series has a built-in programmable timing pattern controller (tpc) that provides pulse outputs by using the 16-bit integrated timer-pulse unit (itu) as a time base. the tpc pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 9.1.1 features tpc features are listed below. 16-bit output data maximum 16-bit data can be output. tpc output can be enabled on a bit-by-bit basis. four output groups output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. selectable output trigger signals output trigger signals can be selected for each group from the compare-match signals of four itu channels. non-overlap mode a non-overlap margin can be provided between pulse outputs. 269 9.1.2 block diagram figure 9-1 shows a block diagram of the tpc. figure 9-1 tpc block diagram paddr ndera tpmr pbddr nderb tpcr internal data bus tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control logic itu compare match signals pulse output pins, group 3 pbdr padr legend tpmr: tpcr: nderb: ndera: pbddr: paddr: ndrb: ndra: pbdr: padr: pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 tpc output mode register tpc output control register next data enable register b next data enable register a port b data direction register port a data direction register next data register b next data register a port b data register port a data register ndrb ndra 270 9.1.3 tpc pins table 9-1 summarizes the tpc output pins. table 9-1 tpc pins name symbol i/o function tpc output 0 tp 0 output group 0 pulse output tpc output 1 tp 1 output tpc output 2 tp 2 output tpc output 3 tp 3 output tpc output 4 tp 4 output group 1 pulse output tpc output 5 tp 5 output tpc output 6 tp 6 output tpc output 7 tp 7 output tpc output 8 tp 8 output group 2 pulse output tpc output 9 tp 9 output tpc output 10 tp 10 output tpc output 11 tp 11 output tpc output 12 tp 12 output group 3 pulse output tpc output 13 tp 13 output tpc output 14 tp 14 output tpc output 15 tp 15 output 271 9.1.4 registers table 9-2 summarizes the tpc registers. table 9-2 tpc registers address * 1 name abbreviation r/w initial value h'ffd1 port a data direction register paddr w h'00 h'ffd3 port a data register padr r/(w) * 2 h'00 h'ffd4 port b data direction register pbddr w h'00 h'ffd6 port b data register pbdr r/(w) * 2 h'00 h'ffa0 tpc output mode register tpmr r/w h'f0 h'ffa1 tpc output control register tpcr r/w h'ff h'ffa2 next data enable register b nderb r/w h'00 h'ffa3 next data enable register a ndera r/w h'00 h'ffa5/ next data register a ndra r/w h'00 h'ffa7 * 3 h'ffa4 next data register b ndrb r/w h'00 h'ffa6 * 3 notes: 1. lower 16 bits of the address. 2. bits used for tpc output cannot be written. 3. the ndra address is h'ffa5 when the same output trigger is selected for tpc output groups 0 and 1 by settings in tpcr. when the output triggers are different, the ndra address is h'ffa7 for group 0 and h'ffa5 for group 1. similarly, the address of ndrb is h'ffa4 when the same output trigger is selected for tpc output groups 2 and 3 by settings in tpcr. when the output triggers are different, the ndrb address is h'ffa6 for group 2 and h'ffa4 for group 3. 272 9.2 register descriptions 9.2.1 port a data direction register (paddr) paddr is an 8-bit write-only register that selects input or output for each pin in port a. port a is multiplexed with pins tp 7 to tp 0 . bits corresponding to pins used for tpc output must be set to 1. for further information about paddr, see section 7.10, port a. 9.2.2 port a data register (padr) padr is an 8-bit readable/writable register that stores tpc output data for groups 0 and 1, when these tpc output groups are used. for further information about padr, see section 7.10, port a. bit initial value read/write 7 pa ddr 0 w port a data direction 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 bit initial value read/write 0 pa 0 r/(w) 0 1 pa 0 r/(w) 1 2 pa 0 r/(w) 2 3 pa 0 r/(w) 3 4 pa 0 r/(w) 4 5 pa 0 r/(w) 5 6 pa 0 r/(w) 6 7 pa 0 r/(w) 7 port a data 7 to 0 these bits store output data for tpc output groups 0 and 1 * ******* note: bits selected for tpc output by ndera settings become read-only bits. * 273 9.2.3 port b data direction register (pbddr) pbddr is an 8-bit write-only register that selects input or output for each pin in port b. port b is multiplexed with pins tp 15 to tp 8 . bits corresponding to pins used for tpc output must be set to 1. for further information about pbddr, see section 7.11, port b. 9.2.4 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores tpc output data for groups 2 and 3, when these tpc output groups are used. for further information about pbdr, see section 7.11, port b. bit initial value read/write 7 pb ddr 0 w port b data direction 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 bit initial value read/write 0 pb 0 r/(w) 0 1 pb 0 r/(w) 1 2 pb 0 r/(w) 2 3 pb 0 r/(w) 3 4 pb 0 r/(w) 4 5 pb 0 r/(w) 5 6 pb 0 r/(w) 6 7 pb 0 r/(w) 7 port b data 7 to 0 these bits store output data for tpc output groups 2 and 3 * ******* note: bits selected for tpc output by nderb settings become read-only bits. * 274 9.2.5 next data register a (ndra) ndra is an 8-bit readable/writable register that stores the next output data for tpc output groups 1 and 0 (pins tp 7 to tp 0 ). during tpc output, when an itu compare match event specified in tpcr occurs, ndra contents are transferred to the corresponding bits in padr. the address of ndra differs depending on whether tpc output groups 0 and 1 have the same output trigger or different output triggers. ndra is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by the same compare match event, the ndra address is h'ffa5. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'ffa7 consists entirely of reserved bits that cannot be modified and always read 1. address h'ffa5 address h'ffa7 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w next data 3 to 0 these bits store the next output data for tpc output group 0 next data 7 to 4 these bits store the next output data for tpc output group 1 bit initial value read/write 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 reserved bits 275 different triggers for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of ndra (group 1) is h'ffa5 and the address of the lower 4 bits (group 0) is h'ffa7. bits 3 to 0 of address h'ffa5 and bits 7 to 4 of address h'ffa7 are reserved bits that cannot be modified and always read 1. address h'ffa5 address h'ffa7 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 1 2 1 1 1 0 1 reserved bits next data 7 to 4 these bits store the next output data for tpc output group 1 bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w next data 3 to 0 these bits store the next output data for tpc output group 0 reserved bits 276 9.2.6 next data register b (ndrb) ndrb is an 8-bit readable/writable register that stores the next output data for tpc output groups 3 and 2 (pins tp 15 to tp 8 ). during tpc output, when an itu compare match event specified in tpcr occurs, ndrb contents are transferred to the corresponding bits in pbdr. the address of ndrb differs depending on whether tpc output groups 2 and 3 have the same output trigger or different output triggers. ndrb is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by the same compare match event, the ndrb address is h'ffa4. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'ffa6 consists entirely of reserved bits that cannot be modified and always read 1. address h'ffa4 address h'ffa6 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w next data 11 to 8 these bits store the next output data for tpc output group 2 next data 15 to 12 these bits store the next output data for tpc output group 3 bit initial value read/write 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 reserved bits 277 different triggers for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of ndrb (group 3) is h'ffa4 and the address of the lower 4 bits (group 2) is h'ffa6. bits 3 to 0 of address h'ffa4 and bits 7 to 4 of address h'ffa6 are reserved bits that cannot be modified and always read 1. address h'ffa4 address h'ffa6 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 1 2 1 1 1 0 1 reserved bits next data 15 to 12 these bits store the next output data for tpc output group 3 bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w next data 11 to 8 these bits store the next output data for tpc output group 2 reserved bits 278 9.2.7 next data enable register a (ndera) ndera is an 8-bit readable/writable register that enables or disables tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. if a bit is enabled for tpc output by ndera, then when the itu compare match event selected in the tpc output control register (tpcr) occurs, the ndra value is automatically transferred to the corresponding padr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndra to padr and the output value does not change. ndera is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ext data enable 7 to 0 (nder7 to nder0): these bits enable or disable tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 tpc outputs tp 7 to tp 0 are disabled (initial value) (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) 1 tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) bit initial value read/write 0 nder0 0 r/w 1 nder1 0 r/w 2 nder2 0 r/w 3 nder3 0 r/w 4 nder4 0 r/w 5 nder5 0 r/w 6 nder6 0 r/w 7 nder7 0 r/w next data enable 7 to 0 these bits enable or disable tpc output groups 1 and 0 279 9.2.8 next data enable register b (nderb) nderb is an 8-bit readable/writable register that enables or disables tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. if a bit is enabled for tpc output by nderb, then when the itu compare match event selected in the tpc output control register (tpcr) occurs, the ndrb value is automatically transferred to the corresponding pbdr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndrb to pbdr and the output value does not change. nderb is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ext data enable 15 to 8 (nder15 to nder8): these bits enable or disable tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bits 7 to 0 nder15 to nder8 description 0 tpc outputs tp 15 to tp 8 are disabled (initial value) (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) 1 tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) bit initial value read/write 0 nder8 0 r/w 1 nder9 0 r/w 2 nder10 0 r/w 3 nder11 0 r/w 4 nder12 0 r/w 5 nder13 0 r/w 6 nder14 0 r/w 7 nder15 0 r/w next data enable 15 to 8 these bits enable or disable tpc output groups 3 and 2 280 9.2.9 tpc output control register (tpcr) tpcr is an 8-bit readable/writable register that selects output trigger signals for tpc outputs on a group-by-group basis. tpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit initial value read/write 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 0 g0cms0 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w group 3 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 3 (tp to tp ) group 2 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 2 (tp to tp ) group 1 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 1 (tp to tp ) group 0 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 0 (tp to tp ) 15 12 11 8 74 30 281 bits 7 and 6?roup 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match event that triggers tpc output group 3 (tp 15 to tp 12 ). bit 7 bit 6 g3cms1 g3cms0 description 0 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in itu channel 0 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in itu channel 1 1 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in itu channel 2 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by (initial value) compare match in itu channel 3 bits 5 and 4?roup 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match event that triggers tpc output group 2 (tp 11 to tp 8 ). bit 5 bit 4 g2cms1 g2cms0 description 0 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in itu channel 0 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in itu channel 1 1 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in itu channel 2 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by (initial value) compare match in itu channel 3 282 bits 3 and 2?roup 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match event that triggers tpc output group 1 (tp 7 to tp 4 ). bit 3 bit 2 g1cms1 g1cms0 description 0 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in itu channel 0 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in itu channel 1 1 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in itu channel 2 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by (initial value) compare match in itu channel 3 bits 1 and 0?roup 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match event that triggers tpc output group 0 (tp 3 to tp 0 ). bit 1 bit 0 g0cms1 g0cms0 description 0 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in itu channel 0 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in itu channel 1 1 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in itu channel 2 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by (initial value) compare match in itu channel 3 283 9.2.10 tpc output mode register (tpmr) tpmr is an 8-bit readable/writable register that selects normal or non-overlapping tpc output for each group. the output trigger period of a non-overlapping tpc output waveform is set in general register b (grb) in the itu channel selected for output triggering. the non-overlap margin is set in general register a (gra). the output values change at compare match a and b. for details see section 9.3.4, non-overlapping tpc output. tpmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?eserved: read-only bits, always read as 1. bit initial value read/write 7 1 6 1 5 1 4 1 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 non-overlap selects non-overlapping tpc output for group 3 (tp to tp ) reserved bits group 2 non-overlap selects non-overlapping tpc output for group 2 (tp to tp ) group 1 non-overlap selects non-overlapping tpc output for group 1 (tp to tp ) group 0 non-overlap selects non-overlapping tpc output for group 0 (tp to tp ) 15 12 11 8 74 30 284 bit 3?roup 3 non-overlap (g3nov): selects normal or non-overlapping tpc output for group 3 (tp 15 to tp 12 ). bit 3 g3nov description 0 normal tpc output in group 3 (output values change at (initial value) compare match a in the selected itu channel) 1 non-overlapping tpc output in group 3 (independent 1 and 0 output at compare match a and b in the selected itu channel) bit 2?roup 2 non-overlap (g2nov): selects normal or non-overlapping tpc output for group 2 (tp 11 to tp 8 ). bit 2 g2nov description 0 normal tpc output in group 2 (output values change at (initial value) compare match a in the selected itu channel) 1 non-overlapping tpc output in group 2 (independent 1 and 0 output at compare match a and b in the selected itu channel) bit 1?roup 1 non-overlap (g1nov): selects normal or non-overlapping tpc output for group 1 (tp 7 to tp 4 ). bit 1 g1nov description 0 normal tpc output in group 1 (output values change at (initial value) compare match a in the selected itu channel) 1 non-overlapping tpc output in group 1 (independent 1 and 0 output at compare match a and b in the selected itu channel) bit 0?roup 0 non-overlap (g0nov): selects normal or non-overlapping tpc output for group 0 (tp 3 to tp 0 ). bit 0 g0nov description 0 normal tpc output in group 0 (output values change at (initial value) compare match a in the selected itu channel) 1 non-overlapping tpc output in group 0 (independent 1 and 0 output at compare match a and b in the selected itu channel) 285 9.3 operation 9.3.1 overview when corresponding bits in paddr or pbddr and ndera or nderb are set to 1, tpc output is enabled. the tpc output initially consists of the corresponding padr or pbdr contents. when a compare-match event selected in tpcr occurs, the corresponding ndra or ndrb bit contents are transferred to padr or pbdr to update the output values. figure 9-2 illustrates the tpc output operation. table 9-3 summarizes the tpc operating conditions. figure 9-2 tpc output operation table 9-3 tpc operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 1 0 generic input port (but the dr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the dr bit) 1 tpc pulse output sequential output of up to 16-bit patterns is possible by writing new output data to ndra and ndrb before the next compare match. for information on non-overlapping operation, see section 9.3.4, non-overlapping tpc output. ddr nder qq tpc output pin dr ndr c qd qd internal data bus output trigger signal 286 9.3.2 output timing if tpc output is enabled, ndra/ndrb contents are transferred to padr/pbdr and output when the selected compare match event occurs. figure 9-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. figure 9-3 timing of transfer of next data register contents and output (example) tcnt gra compare match a signal ndrb pbdr tp to tp 815 n n n m m n + 1 n n 287 9.3.3 normal tpc output sample setup procedure for normal tpc output: figure 9-4 shows a sample procedure for setting up normal tpc output. figure 9-4 setup procedure for normal tpc output (example) normal tpc output set next tpc output data compare match? no yes set next tpc output data itu setup port and tpc setup itu setup 10 11 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. set tior to make gra an output compare register (with output inhibited). set the tpc output trigger period. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tier. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. select the itu compare match event to be used as the tpc output trigger in tpcr. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, set the next output values in the ndr bits. 1 2 3 4 5 6 7 8 select gr functions set gra value select counting operation select interrupt request start counter set initial output data select port output enable tpc output select tpc output trigger 288 example of normal tpc output (example of five-phase pulse output): figure 9-5 shows an example in which the tpc is used for cyclic five-phase pulse output. figure 9-5 normal tpc output example (five-phase pulse output) gra h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 ? ? ? time 80 tcnt tcnt value c0 40 60 20 30 10 18 08 88 80 c0 compare match the itu channel to be used as the output trigger channel is set up so that gra is an output compare register and the counter will be cleared by compare match a. the trigger period is set in gra. the imiea bit is set to 1 in tier to enable the compare match a interrupt. h'f8 is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the itu channel set up in step 1 as the output trigger. output data h'80 is written in ndrb. the timer counter in this itu channel is started. when compare match a occurs, the ndrb contents are transferred to pbdr and output. the compare match/input capture a (imfa) interrupt service routine writes the next output data (h'c0) in ndrb. five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88?at successive imfa interrupts. 00 80 c0 40 60 20 30 10 18 08 88 80 c0 40 289 9.3.4 non-overlapping tpc output sample setup procedure for non-overlapping tpc output: figure 9-6 shows a sample procedure for setting up non-overlapping tpc output. figure 9-6 setup procedure for non-overlapping tpc output (example) non-overlapping tpc output set next tpc output data compare match a? no yes set next tpc output data start counter itu setup port and tpc setup itu setup set initial output data set up tpc output enable tpc transfer select tpc transfer trigger select non-overlapping groups 1 2 3 4 12 10 11 5 6 7 8 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. set tior to make gra and grb output compare registers (with output inhibited). set the tpc output trigger period in grb and the non-overlap margin in gra. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tier. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. in tpcr, select the itu compare match event to be used as the tpc output trigger. in tpmr, select the groups that will operate in non-overlap mode. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, write the next output value in the ndr bits. select gr functions set gr values select counting operation select interrupt requests 290 example of non-overlapping tpc output (example of four-phase complementary non- overlapping output): figure 9-7 shows an example of the use of tpc output for four-phase complementary non-overlapping pulse output. figure 9-7 non-overlapping tpc output example (four-phase complementary non-overlapping pulse output) grb h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 tp 10 tp 9 tp 8 time 95 00 65 95 59 56 95 65 05 65 41 59 50 56 14 95 05 65 tcnt period is set in grb. the non-overlap margin is set in gra. the imiea bit is set to 1 in tier to enable imfa interrupts. h'ff is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set tcnt value non-overlap margin the itu channel to be used as the output trigger channel is set up so that gra and grb are output compare registers and the counter will be cleared by compare match b. the tpc output trigger ? ? ? bits g3nov and g2nov are set to 1 in tpmr to select non-overlapping output. output data h'95 is written in ndrb. the timer counter in this itu channel is started. when compare match b occurs, outputs change from 1 to 0. when compare match a occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of gra). the imfa interrupt service routine writes the next output data (h'65) in ndrb. four-phase complementary non-overlapping pulse output can be obtained by writing h'59, h'56, h'95? at successive imfa interrupts. gra 291 9.3.5 tpc output triggering by input capture tpc output can be triggered by itu input capture as well as by compare match. if gra functions as an input capture register in the itu channel selected in tpcr, tpc output will be triggered by the input capture signal. figure 9-8 shows the timing. figure 9-8 tpc output triggering by input capture (example) tioc pin input capture signal ndr dr n n m 292 9.4 usage notes 9.4.1 operation of tpc output pins tp 0 to tp 15 are multiplexed with itu pin functions. when itu output is enabled, the corresponding pins cannot be used for tpc output. the data transfer from ndr bits to dr bits takes place, however, regardless of the usage of the pin. pin functions should be changed only under conditions in which the output trigger event will not occur. 9.4.2 note on non-overlapping output during non-overlapping operation, the transfer of ndr bit values to dr bits takes place as follows. 1. ndr bits are always transferred to dr bits at compare match a. 2. at compare match b, ndr bits are transferred only if their value is 0. bits are not transferred if their value is 1. figure 9-9 illustrates the non-overlapping tpc output operation. figure 9-9 non-overlapping tpc output ddr nder qq tpc output pin dr ndr c qd qd compare match a compare match b internal data bus 293 therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the imfa interrupt service routine write the next data in ndr, or by having the imfa interrupt activate the dmac. the next data must be written before the next compare match b occurs. figure 9-10 shows the timing relationships. figure 9-10 non-overlapping operation and ndr write timing compare match a compare match b ndr write ndr ndr write dr 0/1 output 0/1 output 0 output 0 output do not write to ndr in this interval do not write to ndr in this interval write to ndr in this interval write to ndr in this interval 294 section 10 watchdog timer 10.1 overview the h8/3032 series has an on-chip watchdog timer (wdt). the wdt has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. as a watchdog timer, it generates a reset signal for the h8/3032 series chip if a system crash allows the timer counter (tcnt) to overflow before being rewritten. in interval timer operation, an interval timer interrupt is requested at each tcnt overflow. 10.1.1 features wdt features are listed below. selection of eight counter clock sources ?2, ?32, ?64, ?128, ?256, ?512, ?2048, or ?4096 interval timer option timer counter overflow generates a reset signal or interrupt. the reset signal is generated in watchdog timer operation. an interval timer interrupt is generated in interval timer operation. watchdog timer reset signal resets the entire h8/3032 series internally, and can also be output externally. the reset signal generated by timer counter overflow during watchdog timer operation resets the entire h8/3032 series internally. an external reset signal can be output from the reso pin to reset other system devices simultaneously. 295 10.1.2 block diagram figure 10-1 shows a block diagram of the wdt. figure 10-1 wdt block diagram 10.1.3 pin configuration table 10-1 describes the wdt output pin. table 10-1 wdt pin name abbreviation i/o function reset output reso output * external output of the watchdog timer reset signal note: * open-drain output. ?2 ?32 ?64 ?128 ?256 ?512 ?2048 ?4096 tcnt tcsr rstcsr reset control interrupt signal reset (internal, external) (interval timer) interrupt control overflow clock clock selector read/ write control internal data bus internal clock sources legend tcnt: tcsr: rstcsr: timer counter timer control/status register reset control/status register 296 10.1.4 register configuration table 10-2 summarizes the wdt registers. table 10-2 wdt registers address * 1 write * 2 read name abbreviation r/w initial value h'ffa8 h'ffa8 timer control/status register tcsr r/(w) * 3 h'18 h'ffa9 timer counter tcnt r/w h'00 h'ffaa h'ffab reset control/status register rstcsr r/(w) * 3 h'3f notes: 1. lower 16 bits of the address. 2. write word data starting at this address. 3. only 0 can be written in bit 7, to clear the flag. 297 10.2 register descriptions 10.2.1 timer counter (tcnt) tcnt is an 8-bit readable and writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from an internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf bit is set to 1 in tcsr. tcnt is initialized to h'00 by a reset and when the tme bit is cleared to 0. note: * tcnt is write-protected by a password. for details see section 10.2.4, notes on register access. bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w 298 10.2.2 timer control/status register (tcsr) tcsr is an 8-bit readable and writable *1 register. its functions include selecting the timer mode and clock source. bits 7 to 5 are initialized to 0 by a reset and in standby mode. bits 2 to 0 are initialized to 0 by a reset. in software standby mode bits 2 to 0 are not initialized, but retain their previous values. notes: 1. tcsr is write-protected by a password. for details see section 10.2.4, notes on register access. 2. only 0 can be written, to clear the flag. bit initial value read/write 7 ovf 0 r/(w) 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w overflow flag status flag indicating overflow clock select these bits select the tcnt clock source timer mode select selects the mode timer enable selects whether tcnt runs or halts reserved bits * 2 299 bit 7?verflow flag (ovf): this status flag indicates that the timer counter has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 in ovf (initial value) 1 [setting condition] set when tcnt changes from h'ff to h'00 bit 6?imer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request when tcnt overflows. if used as a watchdog timer, the wdt generates a reset signal when tcnt overflows. bit 6 wt/ it description 0 interval timer: requests interval timer interrupts (initial value) 1 watchdog timer: generates a reset signal bit 5?imer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt is counting bits 4 and 3?eserved: read-only bits, always read as 1. 300 bits 2 to 0?lock select 2 to 0 (cks2/1/0): these bits select one of eight internal clock sources, obtained by prescaling the system clock (?, for input to tcnt. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 ?2 (initial value) 1 ?32 1 0 ?64 1 ?128 1 0 0 ?256 1 ?512 1 0 ?2048 1 ?4096 10.2.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable and writable *1 register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. bits 7 and 6 are initialized by input of a reset signal at the res pin. they are not initialized by reset signals generated by watchdog timer overflow. notes: 1. rstcsr is write-protected by a password. for details see section 10.2.4, notes on register access. 2. only 0 can be written in bit 7, to clear the flag. bit initial value read/write 7 wrst 0 r/(w) 6 rstoe 0 r/w 5 1 4 1 3 1 0 1 2 1 1 1 * watchdog timer reset indicates that a reset signal has been generated reserved bits reset output enable enables or disables external output of the reset signal 2 301 bit 7?atchdog timer reset (wrst): during watchdog timer operation, this bit indicates that tcnt has overflowed and generated a reset signal. this reset signal resets the entire h8/3003 chip internally. if bit rstoe is set to 1, this reset signal is also output (low) at the reso pin to initialize external system devices. bit 7 wrst description 0 [clearing condition] cleared to 0 by reset signal input at res pin, or by writing 0 (initial value) 1 [setting condition] set when tcnt overflow generates a reset signal during watchdog timer operation bit 6?eset output enable (rstoe): enables or disables external output at the reso pin of the reset signal generated if tcnt overflows during watchdog timer operation. bit 6 rstoe description 0 reset signal is not output externally (initial value) 1 reset signal is output externally bits 5 to 0?eserved: read-only bits, always read as 1. 302 10.2.4 notes on register access the watchdog timer s tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte instructions. figure 10-2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). this transfers the write data from the lower byte to tcnt or tcsr. figure 10-2 format of data written to tcnt and tcsr 15 8 7 0 h'5a write data address h'ffa8 * 15 8 7 0 h'a5 write data address h'ffa8 * tcnt write tcsr write note: lower 16 bits of the address. * 303 writing to rstcsr: rstcsr must be written by a word transfer instruction. it cannot be written by byte transfer instructions. figure 10-3 shows the format of data written to rstcsr. to write 0 in the wrst bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. the h'00 in the lower byte clears the wrst bit in rstcsr to 0. to write to the rstoe bit, the upper byte must contain h'5a and the lower byte must contain the write data. writing this word transfers a write data value into the rstoe bit. figure 10-3 format of data written to rstcsr reading tcnt, tcsr, and rstcsr: these registers are read like other registers. byte access instructions can be used. the read addresses are h'ffa8 for tcsr, h'ffa9 for tcnt, and h'ffab for rstcsr, as listed in table 10-3. table 10-3 read addresses of tcnt, tcsr, and rstcsr address * register h'ffa8 tcsr h'ffa9 tcnt h'ffab rstcsr note: * lower 16 bits of the address. 15 8 7 0 h'a5 write data address h'ffaa * 15 8 7 0 h'5a write data address h'ffaa * writing 0 in wrst bit writing to rstoe bit note: lower 16 bits of the address. * 304 10.3 operation operations when the wdt is used as a watchdog timer and as an interval timer are described below. 10.3.1 watchdog timer operation figure 10-4 illustrates watchdog timer operation. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1 in tcsr. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. if tcnt fails to be rewritten and overflows due to a system crash etc., the h8/3032 series is internally reset for a duration of 518 states. the watchdog reset signal can be externally output from the reso pin to reset external system devices. the reset signal is output externally for 132 states. external output can be enabled or disabled by the rstoe bit in rstcsr. a watchdog reset has the same vector as a reset generated by input at the res pin. software can distinguish a res reset from a watchdog reset by checking the wrst bit in rstcsr. if a res reset and a watchdog reset occur simultaneously, the res reset takes priority. figure 10-4 watchdog timer operation h'ff h'00 reso wdt overflow start h'00 written in tcnt reset tme set to 1 h'00 written in tcnt internal reset signal 518 states 132 states tcnt count value ovf = 1 305 10.3.2 interval timer operation figure 10-5 illustrates interval timer operation. to use the wdt as an interval timer, clear bit wt/ it to 0 and set bit tme to 1 in tcsr. an interval timer interrupt request is generated at each tcnt overflow. this function can be used to generate interval timer interrupts at regular intervals. figure 10-5 interval timer operation tcnt count value time t interval timer interrupt interval timer interrupt interval timer interrupt interval timer interrupt wt/ = 0 tme = 1 it h'ff h'00 306 10.3.3 timing of setting of overflow flag (ovf) figure 10-6 shows the timing of setting of the ovf flag in tcsr. the ovf flag is set to 1 when tcnt overflows. at the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. figure 10-6 timing of setting of ovf tcnt overflow signal ovf h'ff h'00 307 10.3.4 timing of setting of watchdog timer reset bit (wrst) the wrst bit in rstcsr is valid when bits wt/ it and tme are both set to 1 in tcsr. figure 10-7 shows the timing of setting of wrst and the internal reset timing. the wrst bit is set to 1 when tcnt overflows and ovf is set to 1. at the same time an internal reset signal is generated for the entire h8/3032 series chip. this internal reset signal clears ovf to 0, but the wrst bit remains set to 1. the reset routine must therefore clear the wrst bit. figure 10-7 timing of setting of wrst bit and internal reset tcnt overflow signal ovf wrst h'ff h'00 wdt internal reset 308 10.4 interrupts during interval timer operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf bit is set to 1 in tcsr. 10.5 usage notes contention between tcnt write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to tcnt, the write takes priority and the timer count is not incremented. see figure 10-8. figure 10-8 contention between tcnt write and increment changing cks2 to cks0 values: halt tcnt by clearing the tme bit to 0 in tcsr before changing the values of bits cks2 to cks0. tcnt tcnt nm counter write data t 3 t 2 t 1 write cycle: cpu writes to tcnt internal write signal tcnt input clock 309 310 section 11 serial communication interface 11.1 overview the h8/3032 series has a serial communication interface (sci). the sci can communicate in asynchronous mode or synchronous mode, and has a multiprocessor communication function for serial communication among two or more processors. 11.1.1 features sci features are listed below. selection of asynchronous or synchronous mode for serial communication a. asynchronous mode serial data communication is synchronized one character at a time. the sci can communicate with a universal asynchronous receiver/transmitter (uart), asynchronous communication interface adapter (acia), or other chip that employs standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity bit: even, odd, or none multiprocessor bit: 1 or 0 receive error detection: parity, overrun, and framing errors break detection: by reading the rxd level directly when a framing error occurs b. synchronous mode serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. there is one serial data communication format. data length: 8 bits receive error detection: overrun errors 311 full duplex communication the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. the transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. built-in baud rate generator with selectable bit rates selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the sck pin. four types of interrupts transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. 312 11.1.2 block diagram figure 11-1 shows a block diagram of the sci. figure 11-1 sci block diagram rxd txd sck rdr rsr tdr tsr ssr scr smr brr module data bus bus interface internal data bus transmit/ receive control baud rate generator ?4 ?16 ?64 clock parity generate parity check tei txi rxi eri legend external clock rsr: rdr: tsr: tdr: smr: scr: ssr: brr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register 313 11.1.3 input/output pins the sci has serial pins for each channel as listed in table 11-1. table 11-1 sci pins name abbreviation i/o function serial clock pin sck input/output sci clock input/output receive data pin rxd input sci receive data input transmit data pin txd output sci transmit data output 11.1.4 register configuration the sci has internal registers as listed in table 11-2. these registers select asynchronous or synchronous mode, specify the data format and bit rate, and control the transmitter and receiver sections. table 11-2 registers channel address * 1 name abbreviation r/w initial value 0 h'ffb0 serial mode register smr r/w h'00 h'ffb1 bit rate register brr r/w h'ff h'ffb2 serial control register scr r/w h'00 h'ffb3 transmit data register tdr r/w h'ff h'ffb4 serial status register ssr r/(w) * 2 h'84 h'ffb5 receive data register rdr r h'00 1 h'ffb8 serial mode register smr r/w h'00 h'ffb9 bit rate register brr r/w h'ff h'ffba serial control register scr r/w h'00 h'ffbb transmit data register tdr r/w h'ff h'ffbc serial status register ssr r/(w) * 2 h'84 h'ffbd receive data register rdr r h'00 notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear flags. 314 11.2 register descriptions 11.2.1 receive shift register (rsr) rsr is the register that receives serial data. the sci loads serial data input at the rxd pin into rsr in the order received, lsb (bit 0) first, thereby converting the data to parallel data. when 1 byte has been received, it is automatically transferred to rdr. the cpu cannot read or write rsr directly. 11.2.2 receive data register (rdr) rdr is the register that stores received serial data. when the sci finishes receiving 1 byte of serial data, it transfers the received data from rsr into rdr for storage. rsr is then ready to receive the next data. this double buffering allows data to be received continuously. rdr is a read-only register. its contents cannot be modified by the cpu. rdr is initialized to h'00 by a reset and in standby mode. bit initial value read/write 7 6 5 4 3 0 2 1 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r 315 11.2.3 transmit shift register (tsr) tsr is the register that transmits serial data. the sci loads transmit data from tdr into tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from tdr into tsr and starts transmitting it. if the tdre flag is set to 1 in ssr, however, the sci does not load the tdr contents into tsr. the cpu cannot read or write tsr directly. 11.2.4 transmit data register (tdr) tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it moves transmit data written in tdr from tdr into tsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in tdr during serial transmission from tsr. the cpu can always read and write tdr. tdr is initialized to h'ff by a reset and in standby mode. bit initial value read/write 7 6 5 4 3 0 2 1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w 316 11.2.5 serial mode register (smr) smr is an 8-bit register that specifies the sci serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write smr. smr is initialized to h'00 by a reset and in standby mode. bit initial value read/write 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w communication mode selects asynchronous or synchronous mode clock select 1/0 these bits select the baud rate generator? clock source character length selects character length in asynchronous mode parity enable selects whether a parity bit is added parity mode selects even or odd parity stop bit length selects the stop bit length multiprocessor mode selects the multiprocessor function 317 bit 7?ommunication mode (c/ a ): selects whether the sci operates in asynchronous or synchronous mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 synchronous mode bit 6?haracter length (chr): selects 7-bit or 8-bit data length in asynchronous mode. in synchronous mode the data length is 8 bits regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) in tdr is not transmitted. bit 5?arity enable (pe): in asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. in synchronous mode the parity bit is neither added nor checked, regardless of the pe setting. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selected by the o/ e bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the o/ e bit. 318 bit 4?arity mode (o/ e ): selects even or odd parity. the o/ e bit setting is valid in asynchronous mode when the pe bit is set to 1 to enable the adding and checking of a parity bit. the o/ e setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. bit 3?top bit length (stop): selects one or two stop bits in asynchronous mode. this setting is used only in asynchronous mode. in synchronous mode no stop bit is added, so the stop bit setting is ignored. bit 3 stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. one stop bit (with value 1) is added at the end of each transmitted character. 2. two stop bits (with value 1) are added at the end of each transmitted character. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit. if the second stop bit is 0 it is treated as the start bit of the next incoming character. 319 bit 2?ultiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, parity settings made by the pe and o/ e bits are ignored. the mp bit setting is valid only in asynchronous mode. it is ignored in synchronous mode. for further information on the multiprocessor communication function, see section 11.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?lock select 1 and 0 (cks1/0): these bits select the clock source of the on-chip baud rate generator. four clock sources are available: ? ?4, ?16, and ?64. for the relationship between the clock source, bit rate register setting, and baud rate, see section 11.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 0 0 (initial value) 0 1 ?4 1 0 ?16 1 1 ?64 320 11.2.6 serial control register (scr) scr enables the sci transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. the cpu can always read and write scr. scr is initialized to h'00 by a reset and in standby mode. bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w transmit interrupt enable enables or disables transmit-data-empty interrupts (txi) clock enable 1/0 these bits select the sci clock source receive interrupt enable enables or disables receive-data-full interrupts (rxi) and receive-error interrupts (eri) transmit enable enables or disables the transmitter receive enable enables or disables the receiver multiprocessor interrupt enable enables or disables multiprocessor interrupts transmit end interrupt enable enables or disables transmit- end interrupts (tei) 321 bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the tdre flag in ssr is set to 1 due to transfer of serial transmit data from tdr to tsr. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * txi interrupt requests can be cleared by reading the value 1 from the tdre flag, then clearing it to 0; or by clearing the tie bit to 0. bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the rdrf flag is set to 1 in ssr due to transfer of serial receive data from rsr to rdr; also enables or disables the receive-error interrupt (eri). bit 6 rie description 0 receive-end (rxi) and receive-error (eri) interrupt requests are disabled (initial value) 1 receive-end (rxi) and receive-error (eri) interrupt requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the value 1 from the rdrf, fer, per, or orer flag, then clearing it to 0; or by clearing the rie bit to 0. bit 5?ransmit enable (te): enables or disables the start of sci serial transmitting operations. bit 5 te description 0 transmitting disabled * 1 (initial value) 1 transmitting enabled * 2 notes: 1. the tdre bit is locked at 1 in ssr. 2. in the enabled state, serial transmitting starts when the tdre bit in ssr is cleared to 0 after writing of transmit data into tdr. select the transmit format in smr before setting the te bit to 1. 322 bit 4?eceive enable (re): enables or disables the start of sci serial receiving operations. bit 4 re description 0 receiving disabled * 1 (initial value) 1 receiving enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags. these flags retain their previous values. 2. in the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. select the receive format in smr before setting the re bit to 1. bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is valid only in asynchronous mode, and only if the mp bit is set to 1 in smr. the mpie setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) [clearing conditions] the mpie bit is cleared to 0. mpb = 1 in received data. 1 multiprocessor interrupts are enabled * receive-data-full interrupts (rxi), receive-error interrupts (eri), and setting of the rdrf, fer, and orer status flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * the sci does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in ssr. when it receives data in which mpb = 1, the sci sets the mpb bit to 1 in ssr, automatically clears the mpie bit to 0, enables rxi and eri interrupts (if the rie bit is set to 1 in scr), and allows the fer and orer flags to be set. 323 bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain new transmit data when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt requests (tei) are disabled * (initial value) 1 transmit-end interrupt requests (tei) are enabled * note: * tei interrupt requests can be cleared by reading the value 1 from the tdre flag in ssr, then clearing the tdre flag to 0, thereby also clearing the tend flag to 0; or by clearing the teie bit to 0. bits 1 and 0?lock enable 1 and 0 (cke1/0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the settings of cke1 and cke0, the sck pin can be used for generic input/output, serial clock output, or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci operating mode in smr before setting the cke1 and cke0 bits. for further details on selection of the sci clock source, see table 11-9 in section 11.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock, sck pin available for generic input/output * 1 synchronous mode internal clock, sck pin used for serial clock output * 1 0 1 asynchronous mode internal clock, sck pin used for clock output * 2 synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input notes: 1. initial value 2. the output clock frequency is the same as the bit rate. 3. the input clock frequency is 16 times the bit rate. 324 11.2.7 serial status register (ssr) ssr is an 8-bit register containing multiprocessor bit values, and status flags that indicate sci operating status. bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r transmit data register empty status flag indicating that transmit data has been transferred from tdr into tsr and new data can be written in tdr multiprocessor bit transfer value of multi- processor bit to be transmitted receive data register full status flag indicating that data has been received and stored in rdr overrun error status flag indicating detection of a receive overrun error framing error status flag indicating detection of a receive framing error parity error status flag indicating detection of a receive parity error transmit end status flag indicating end of transmission * note: only 0 can be written, to clear the flag. * **** multiprocessor bit stores the received multiprocessor bit value 325 the cpu can always read and write ssr, but cannot write 1 in the tdre, rdrf, orer, per, and fer flags. these flags can be cleared to 0 only if they have first been read while set to 1. the tend and mpb flags are read-only bits that cannot be written. ssr is initialized to h'84 by a reset and in standby mode. bit 7?ransmit data register empty (tdre): indicates that the sci has loaded transmit data from tdr into tsr and the next serial transmit data can be written in tdr. bit 7 tdre description 0 tdr contains valid transmit data [clearing conditions] software reads tdre while it is set to 1, then writes 0. 1 tdr does not contain valid transmit data (initial value) [setting conditions] the chip is reset or enters standby mode. the te bit in scr is cleared to 0. tdr contents are loaded into tsr, so new data can be written in tdr. bit 6?eceive data register full (rdrf): indicates that rdr contains new receive data. bit 6 rdrf description 0 rdr does not contain new receive data (initial value) [clearing conditions] the chip is reset or enters standby mode. software reads rdrf while it is set to 1, then writes 0. the dmac reads data from rdr. 1 rdr contains new receive data [setting condition] when serial data is received normally and transferred from rsr to rdr. note: the rdr contents and rdrf flag are not affected by detection of receive errors or by clearing of the re bit to 0 in scr. they retain their previous values. if the rdrf flag is still set to 1 when reception of the next data ends, an overrun error occurs and receive data is lost. 326 bit 5?verrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5 orer description 0 receiving is in progress or has ended normally (initial value) * 1 [clearing conditions] the chip is reset or enters standby mode. software reads orer while it is set to 1, then writes 0. 1 a receive overrun error occurred * 2 [setting condition] reception of the next serial data ends when rdrf = 1. notes: 1. clearing the re bit to 0 in scr does not affect the orer flag, which retains its previous value. 2. rdr continues to hold the receive data before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while the orer flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 4?raming error (fer): indicates that data reception ended abnormally due to a framing error in asynchronous mode. bit 4 fer description 0 receiving is in progress or has ended normally (initial value) * 1 [clearing conditions] the chip is reset or enters standby mode. software reads fer while it is set to 1, then writes 0. 1 a receive framing error occurred * 2 [setting condition] the stop bit at the end of receive data is checked and found to be 0. notes: 1. clearing the re bit to 0 in scr does not affect the fer flag, which retains its previous value. 2. when the stop bit length is 2 bits, only the first bit is checked. the second stop bit is not checked. when a framing error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the fer flag is set to 1. in synchronous mode, serial transmitting is also disabled. 327 bit 3?arity error (per): indicates that data reception ended abnormally due to a parity error in asynchronous mode. bit 3 per description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] the chip is reset or enters standby mode. software reads per while it is set to 1, then writes 0. 1 a receive parity error occurred * 2 [setting condition] the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of o/ e in smr. notes: 1. clearing the re bit to 0 in scr does not affect the per flag, which retains its previous value. 2. when a parity error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the per flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 2?ransmit end (tend): indicates that when the last bit of a serial character was transmitted tdr did not contain new transmit data, so transmission has ended. the tend flag is a read-only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing conditions] software reads tdre while it is set to 1, then writes 0 in the tdre flag. 1 end of transmission (initial value) [setting conditions] the chip is reset or enters standby mode. the te bit is cleared to 0 in scr. tdre is 1 when the last bit of a serial character is transmitted. 328 bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. mpb is a read-only bit and cannot be written. bit 1 mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if the re bit is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. the mpbt setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 11.2.8 bit rate register (brr) brr is an 8-bit register that, together with the cks1 and cks0 bits in smr that select the baud rate generator clock source, determines the serial communication bit rate. the cpu can always read and write brr. brr is initialized to h'ff by a reset and in standby mode. the two sci channels have independent baud rate generator control, so different values can be set in the two channels. table 11-3 shows examples of brr settings in asynchronous mode. table 11-4 shows examples of brr settings in synchronous mode. bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w 329 table 11-3 examples of bit rates and brr settings in asynchronous mode ?(mhz) 2 2.097152 2.4576 3 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 1 141 0.03 1 148 ?.04 1 174 ?.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0 0 155 0.16 1200 0 51 0.16 0 54 ?.70 0 63 0 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0 0 38 0.16 4800 0 12 0.16 0 13 ?.48 0 15 0 0 19 ?.34 9600 0 6 ?.99 0 6 ?.48 0 7 0 0 9 ?.34 19200 0 2 8.51 0 2 13.78 0 3 0 0 4 ?.34 31250 0 1 0 0 1 4.86 0 1 22.88 0 2 0 38400 0 1 ?8.62 0 1 ?4.67 0 1 0 ?(mhz) 3.6864 4 4.9152 5 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?.25 150 1 191 0 1 207 0.16 1 255 0 2 64 0.16 300 1 95 0 1 103 0.16 1 127 0 1 129 0.16 600 0 191 0 0 207 0.16 0 255 0 1 64 0.16 1200 0 95 0 0 103 0.16 0 127 0 0 129 0.16 2400 0 47 0 0 51 0.16 0 63 0 0 64 0.16 4800 0 23 0 0 25 0.16 0 31 0 0 32 ?.36 9600 0 11 0 0 12 0.16 0 15 0 0 15 1.73 19200 0 5 0 0 6 ?.99 0 7 0 0 7 1.73 31250 0 3 0 0 4 ?.70 0 4 0 38400 0 2 0 0 2 8.51 0 3 0 0 3 1.73 330 table 11-3 examples of bit rates and brr settings in asynchronous mode (cont) ?(mhz) 6 6.144 7.3728 8 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 106 ?.44 2 108 0.08 2 130 ?.07 2 141 0.03 150 2 77 0.16 2 79 0 2 95 0 2 103 0.16 300 1 155 0.16 1 159 0 1 191 0 1 207 0.16 600 1 77 0.16 1 79 0 1 95 0 1 103 0.16 1200 0 155 0.16 0 159 0 0 191 0 0 207 0.16 2400 0 77 0.16 0 79 0 0 95 0 0 103 0.16 4800 0 38 0.16 0 39 0 0 47 0 0 51 0.16 9600 0 19 ?.34 0 19 0 0 23 0 0 25 0.16 19200 0 9 ?.34 0 9 0 0 11 0 0 12 0.16 31250 0 5 0 0 5 2.40 0 6 5.33 0 7 0 38400 0 4 ?.34 0 4 0 0 5 0 0 6 ?.99 ?(mhz) 9.8304 10 12 12.288 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 174 ?.26 2 177 ?.25 2 212 0.03 2 217 0.08 150 2 127 0 2 129 0.16 2 155 0.16 2 159 0 300 1 255 0 2 64 0.16 2 77 0.16 2 79 0 600 1 127 0 1 129 0.16 1 155 0.16 1 159 0 1200 0 255 0 1 64 0.16 1 77 0.16 1 79 0 2400 0 127 0 0 129 0.16 0 155 0.16 0 159 0 4800 0 63 0 0 64 0.16 0 77 0.16 0 79 0 9600 0 31 0 0 32 ?.36 0 38 0.16 0 39 0 19200 0 15 0 0 15 1.73 0 19 ?.34 0 19 0 31250 0 9 ?.70 0 9 0 0 11 0 0 11 2.40 38400 0 7 0 0 7 1.73 0 9 ?.34 0 9 0 331 table 11-3 examples of bit rates and brr settings in asynchronous mode (cont) ?(mhz) 14 14.7456 16 bit rate error error error (bits/s) n n (%) n n (%) n n (%) 110 2 248 ?.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0 2 207 0.16 300 2 90 0.16 2 95 0 2 103 0.16 600 1 181 0.16 1 191 0 1 207 0.16 1200 1 90 0.16 1 95 0 1 103 0.16 2400 0 181 0.16 0 191 0 0 207 0.16 4800 0 90 0.16 0 95 0 0 103 0.16 9600 0 45 ?.93 0 47 0 0 51 0.16 19200 0 22 ?.93 0 23 0 0 25 0.16 31250 0 13 0 0 14 ?.70 0 15 0 38400 0 10 3.57 0 11 0 0 12 0.16 332 table 11-4 examples of bit rates and brr settings in synchronous mode ?(mhz) 24 81016 nn nn nn nn nn 110 3 70 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 2.5 k 0 199 1 99 1 199 1 249 2 99 5 k 0 99 0 199 1 99 1 124 1 199 10 k 0 49 0 99 0 199 0 249 1 99 25 k 0 19 0 39 0 79 0 99 0 159 50 k 0 9 0 19 0 39 0 49 0 79 100 k 0 4 0 9 0 19 0 24 0 39 250 k 0 1 0 3 0 7 0 9 0 15 500 k 0 0 * 01 03 04 07 1 m 0 0 * 01 03 2 m 0 0 * 0 1 2.5 m 0 0 * 4 m 0 0 * note: settings with an error of 1% or less are recommended. legend blank: no setting available ? setting possible, but error occurs * : continuous transmit/receive not possible the brr setting is calculated as follows: asynchronous mode: n = 10 6 e 1 synchronous mode: n = 10 6 e 1 b: bit rate (bits/s) n: brr setting for baud rate generator (0 n 255) ?: system clock frequency (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see the table below.) bit rate (bits/s) 64 2 2ne1 b ? 8 2 2ne1 b 333 smr settings n clock source cks1 cks0 0 0 0 1 ?4 0 1 2 ?16 1 0 3 ?64 1 1 the bit rate error in asynchronous mode is calculated as follows. error (%) = ? 100 ? 10 6 (n + 1) b 64 2 2ne1 334 table 11-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. tables 11-6 and 11-7 indicate the maximum bit rates with external clock input. table 11-5 maximum bit rates for various frequencies (asynchronous mode) settings ?(mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 335 table 11-6 maximum bit rates with external clock input (asynchronous mode) ?(mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 336 table 11-7 maximum bit rates with external clock input (synchronous mode) ?(mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 337 11.3 operation 11.3.1 overview the sci has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. serial communication is possible in either mode. asynchronous or synchronous mode and the communication format are selected in smr, as shown in table 11-8. the sci clock source is selected by the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 11-9. asynchronous mode data length is selectable: 7 or 8 bits. parity and multiprocessor bits are selectable. so is the stop bit length (1 or 2 bits). these selections determine the communication format and character length. in receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. an internal or external clock can be selected as the sci clock source. when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode the communication format has a fixed 8-bit data length. in receiving, it is possible to detect overrun errors. an internal or external clock can be selected as the sci clock source. when an internal clock is selected, the sci operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used. 338 table 11-8 smr settings and serial communication formats sci communication format multi- stop bit 7 bit 6 bit 2 bit 5 bit 3 data processor parity bit c/ a chr mp pe stop mode length bit bit length 00000 8-bit data absent absent 1 bit 00001 2 bits 00010 present 1 bit 00011 2 bits 01000 7-bit data absent 1 bit 01001 2 bits 01010 present 1 bit 01011 2 bits 001 0 8-bit data present absent 1 bit 001 1 2 bits 011 0 7-bit data 1 bit 011 1 2 bits 1 synchronous 8-bit data absent none mode table 11-9 smr and scr settings and sci clock source selection smr scr settings bit 7 bit 1 bit 0 c/ a cke1 cke0 mode clock source sck pin function 0 0 0 asynchronous mode internal sci does not use the sck pin 0 0 1 outputs a clock with frequency matching the bit rate 0 1 0 external 01 1 1 0 0 synchronous mode internal outputs the serial clock 10 1 1 1 0 external inputs the serial clock 11 1 smr settings asynchronous mode asynchronous mode (multi- processor format) sci transmit/receive clock inputs a clock with frequency 16 times the bit rate 339 11.3.2 operation in asynchronous mode in asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full duplex communication is possible. the transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 11-2 shows the general format of asynchronous serial communication. in asynchronous serial communication the communication line is normally held in the mark (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in asynchronous mode, the sci synchronizes at the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. figure 11-2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) serial data 0 1 1 1 idle (mark) state 1 d0 d1 d2 d3 d4 d5 d6 d7 0/1 (lsb) (msb) start bit transmit or receive data parity bit stop bit one unit of data (character or frame) 1 bit 7 bits or 8 bits 1 bit or no bit 1 bit or 2 bits 340 communication formats: table 11-10 shows the 12 communication formats that can be selected in asynchronous mode. the format is selected by settings in smr. table 11-10 serial communication formats (asynchronous mode) 123456789101112 8-bit data stop 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8 bit data 8 bit data 7-bit data 7-bit data s s s s s s s s s s s s stop stop p stop p stop stop stop stop stop stop stop stop p p mpb stop stop stop mpb mpb mpb stop stop legend s: stop: p: mpb: start bit stop bit parity bit multiprocessor bit chr pe mp stop smr settings 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 serial communication format and frame length stop 341 clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in smr and bits cke1 and cke0 in scr. see table 11-9. when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the sci operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as in figure 11-3 so that the rising edge of the clock occurs at the center of each transmit data bit. figure 11-3 phase relationship between output clock and serial data (asynchronous mode) transmitting and receiving data sci initialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and rdr, which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 11-4 is a sample flowchart for initializing the sci. 0 d0d1d2d3d4d5d6d7o/i 1 1 1 frame 342 figure 11-4 sample flowchart for sci initialization clear te and re bits to 0 in scr transmitting or receiving no yes 1. 2. 3. 4. select the communication format in smr. write the value corresponding to the bit rate in brr. this step is not necessary when an external clock is used. select communication format in smr 1 set value in brr 2 3 set te or re bit to 1 in scr set rie, tie, teie, and mpie bits as necessary 4 1 bit interval elapsed? wait wait for at least the interval required to transmit or receive 1 bit, then set the te or re bit to 1 in scr. set the rie, tie, teie, and mpie bits as necessary. setting the te or re bit enables the sci to use the txd or rxd pin. start of initialization set cke1 and cke0 bits in scr (leaving te and re bits cleared to 0) select the clock source in scr. clear the rie, tie, teie, mpie, te, and re bits to 0. if clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in scr. 343 transmitting serial data (asynchronous mode): figure 11-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. figure 11-5 sample flowchart for transmitting serial data start transmitting read tdre flag in ssr tdre = 1? write transmit data in tdr and clear tdre flag to 0 in ssr all data transmitted? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read ssr, check that the tdre flag is 1, then write transmit data in tdr and clear the tdre flag to 0. read tend flag in ssr tend = 1? no yes output break signal? no yes clear te bit to 0 in scr 4 1. 2. 3. 4. clear dr bit to 0, set ddr bit to 1 initialize to continue transmitting serial data: after checking that the tdre flag is 1, indicating that data can be written, write data in tdr, then clear the tdre flag to 0. to output a break signal at the end of serial transmission: set the ddr bit to 1 and clear the dr bit to 0 (ddr and dr are i/o port registers), then clear the te bit to 0 in scr. 344 in transmitting serial data, the sci operates as follows. the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0 the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. after loading the data from tdr into tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: start bit: one 0 bit is output. transmit data: 7 or 8 bits are output, lsb first. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. stop bit: one or two 1 bits (stop bits) are output. mark state: output of 1 bits continues until the start bit of the next transmit data. the sci checks the tdre flag when it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time. figure 11-6 shows an example of sci transmit operation in asynchronous mode. figure 11-6 example of sci transmit operation in asynchronous mode (8-bit data with parity and 1 stop bit) 1 start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit 1 idle (mark) state tdre tend txi interrupt request txi interrupt handler writes data in tdr and clears tdre flag to 0 txi interrupt request 1 frame tei interrupt request 345 receiving serial data (asynchronous mode): figure 11-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. figure 11-7 sample flowchart for receiving serial data (1) start receiving read rdrf flag in ssr rdrf = 1? read receive data from rdr, and clear rdrf flag to 0 in ssr per rer orer = 1? clear re bit to 0 in scr finished receiving? end error handling (continued on next page) 1 4 no yes yes no no yes 1. 2., 3. 4. 5. sci initialization: the receive data function of the rxd pin is selected automatically. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after executing the necessary error handling, clear the orer, per, and fer flags all to 0. receiving cannot resume if any of the orer, per, and fer flags remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. sci status check and receive data read: read ssr, check that rdrf is set to 1, then read receive data from rdr and clear the rdrf flag to 0. notification that the rdrf flag has changed from 0 to 1 can also be given by the rxi interrupt. to continue receiving serial data: check the rdrf flag, read rdr, and clear the rdrf flag to 0 before the stop bit of the current frame is received. read orer, per, and fer flags in ssr 2 5 initialize 3 346 figure 11-7 sample flowchart for receiving serial data (2) no no no no yes yes yes yes framing error handling per = 1? orer = 1? overrun error handling fer = 1? break? error handling parity error handling clear orer, per, and fer flags to 0 in ssr clear re bit to 0 in scr end 3 347 in receiving, the sci operates as follows. the sci monitors the receive data line. when it detects a start bit, the sci synchronizes internally and starts receiving. receive data is stored in rsr in order from lsb to msb. the parity bit and stop bit are received. after receiving, the sci makes the following checks: parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in smr. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. status check: the rdrf flag must be 0 so that receive data can be transferred from rsr into rdr. if these checks all pass, the rdrf flag is set to 1 and the received data is stored in rdr. if one of the checks fails (receive error), the sci operates as indicated in table 11-11. note: when a receive error occurs, further receiving is disabled. in receiving, the rdrf flag is not set to 1. be sure to clear the error flags. when the rdrf flag is set to 1, if the rie bit is set to 1 in scr, a receive-data-full interrupt (rxi) is requested. if the orer, per, or fer flag is set to 1 and the rie bit in scr is also set to 1, a receive-error interrupt (eri) is requested. table 11-11 receive error conditions receive error abbreviation condition data transfer overrun error orer receiving of next data ends receive data not transferred while rdrf flag is still set to from rsr to rdr 1 in ssr framing error fer stop bit is 0 receive data transferred from rsr to rdr parity error per parity of receive data differs receive data transferred from even/odd parity setting from rsr to rdr in smr 348 figure 11-8 shows an example of sci receive operation in asynchronous mode. figure 11-8 example of sci receive operation (8-bit data with parity and one stop bit) 11.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id continues to receive further incoming data. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 11-9 shows an example of communication among different processors using a multiprocessor format. 1 start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit start bit 0 d0 d1 d7 0/1 stop bit 1 data parity bit 1 idle (mark) state rdrf fer rxi request 1 frame framing error, eri request rxi interrupt handler reads data in rdr and clears rdrf flag to 0 349 communication formats: four formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 11-8. clock: see the description of asynchronous mode. figure 11-9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting processor receiving processor a serial communication line receiving processor b receiving processor c receiving processor d (id = 01) (id = 02) (id = 03) (id = 04) serial data h'01 h'aa (mpb = 1) (mpb = 0) id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id legend mpb: multiprocessor bit 350 transmitting and receiving data transmitting multiprocessor serial data: figure 11-10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. figure 11-10 sample flowchart for transmitting multiprocessor serial data no no no no yes yes yes yes initialize start transmitting read tdre flag in ssr tdre = 1? write transmit data in tdr and set mpbt bit in ssr clear tdre flag to 0 all data transmitted? read tend flag in ssr tend = 1? 1 2 3 4 1. 2. 3. 4. sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read ssr, check that the tdre flag is 1, then write transmit data in tdr. also set the mpbt flag to 0 or 1 in ssr. finally, clear the tdre flag to 0. to continue transmitting serial data: after checking that the tdre flag is 1, indicating that data can be written, write data in tdr, then clear the tdre flag to 0. to output a break signal at the end of serial transmission: set the ddr bit to 1 and clear the dr bit to 0 (ddr and dr are i/o port registers), then clear the te bit to 0 in scr. output break signal? clear dr bit to 0, set ddr bit to 1 clear te bit to 0 in scr end 351 in transmitting serial data, the sci operates as follows. the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0 the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. after loading the data from tdr into tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit in scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: start bit: one 0 bit is output. transmit data: 7 or 8 bits are output, lsb first. multiprocessor bit: one multiprocessor bit (mpbt value) is output. stop bit: one or two 1 bits (stop bits) are output. mark state: output of 1 bits continues until the start bit of the next transmit data. the sci checks the tdre flag when it outputs the stop bit. if the tdre flag is 0, the sci loads data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag in ssr to 1, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time. figure 11-11 shows an example of sci transmit operation using a multiprocessor format. figure 11-11 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit) 1 start bit 0 d0 d1 d7 0/1 stop bit 1 data multi- processor bit start bit 0 d0 d1 d7 0/1 stop bit 1 data 1 idle (mark) state tdre tend txi request txi interrupt handler writes data in tdr and clears tdre flag to 0 txi request 1 frame tei request serial data multi- processor bit 352 receiving multiprocessor serial data: figure 11-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. figure 11-12 sample flowchart for receiving multiprocessor serial data (1) initialize start receiving read rdrf flag in ssr rdrf = 1? read receive data from rdr read orer and fer flags in ssr fer orer = 1 read rdrf flag in ssr rdrf = 1? read receive data from rdr finished receiving? clear re bit to 0 in scr error handling (continued on next page) end 1 2 4 5 1. 2. 3. 4. 5. sci initialization: the receive data function of the rxd pin is selected automatically. id receive cycle: set the mpie bit to 1 in scr. sci status check and id check: read ssr, check that the rdrf flag is set to 1, then read data from rdr and compare with the processor? own id. if the id does not match, set the mpie bit to 1 again and clear the rdrf flag to 0. if the id matches, clear the rdrf flag to 0. sci status check and data receiving: read ssr, check that the rdrf flag is set to 1, then read data from rdr. receive error handling and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after executing the necessary error handling, clear the orer and fer flags both to 0. receiving cannot resume while either the orer or fer flag remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. yes yes yes no yes no yes no no no 3 set mpie bit to 1 in scr read orer and fer flags in ssr yes fer prer = 1 own id? no no 353 figure 11-12 sample flowchart for receiving multiprocessor serial data (2) no no yes no yes yes error handling orer = 1? overrun error handling fer = 1? break? framing error handling clear orer, per, and fer flags to 0 in ssr clear re bit to 0 in scr end 5 354 figure 11-13 shows an example of sci receive operation using a multiprocessor format. figure 11-13 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit) 1 start bit 0 d0 d1 d7 1 stop bit 1 data (id1) mpb start bit 0 d0 d1 d7 0 stop bit 1 data (data1) mpb 1 idle (mark) state mpie rdrf rdr value id1 rxi request (multiprocessor interrupt), mpie = 0 rxi handler reads rdr data and clears rdrf flag to 0 not own id, so mpie bit is set to 1 again no rxi request, rdr not updated a. own id does not match data 1 start bit 0 d0 d1 d7 1 stop bit 1 data (id2) mpb start bit 0 d0 d1 d7 0 stop bit 1 data (data2) mpb 1 idle (mark) state mpie rdrf rdr value id2 rxi request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads rdr data and clears rdrf flag to 0 own id, so receiving continues, with data received by rxi interrupt handler mpie bit is set to 1 again b. own id matches data id1 data 2 355 11.3.4 synchronous operation in synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 11-14 shows the general format in synchronous serial communication. figure 11-14 data format in synchronous communication in synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in each character, the serial data bits are transmitted in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode the sci receives data by synchronizing with the rise of the serial clock. communication format: the data length is fixed at 8 bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by clearing or setting the cke1 bit in scr. see table 11-9. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high state. when the sci is only receiving, it receives in units of two characters, so it outputs 16 clock pulses. to receive in units of one character, an external clock source must be selected. serial clock serial data bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb don? care don? care one unit (character or frame) of serial data transfer direction * * note: high except in continuous transmitting or receiving * 356 transmitting and receiving data sci initialization (synchronous mode): before transmitting or receiving, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing the te bit to 0 sets the tdre flag to 1 and initializes tsr. clearing the re bit to 0, however, does not initialize the rdrf, per, fer, and ore flags and rdr, which retain their previous contents. figure 11-15 is a sample flowchart for initializing the sci. figure 11-15 sample flowchart for sci initialization clear te and re bits to 0 in scr 1 bit interval elapsed? start transmitting or receiving no yes 1. 2. 3. 4. select the clock source in scr. clear the rie, tie, teie, mpie, te, and re bits to 0. select the communication format in smr. write the value corresponding to the bit rate in brr. this step is not necessary when an external clock is used. 1 2 set rie, tie, teie, mpie, cke1, and cke0 bits in scr (leaving te and re bits cleared to 0) 3 set te or re to 1 in scr set rie, tie, teie, and mpie bits as necessary 4 wait wait for at least the interval required to transmit or receive one bit, then set the te or re bit to 1 in scr. also set the rie, tie, teie, and mpie bits as necessary. setting the te or re bit enables the sci to use the txd or rxd pin. start of initialization set value in brr select communication format in smr 357 transmitting serial data (synchronous mode): figure 11-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. figure 11-16 sample flowchart for serial transmitting start transmitting read tdre flag in ssr tdre = 1? write transmit data in tdr and clear tdre flag to 0 in ssr end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read ssr, check that the tdre flag is 1, then write transmit data in tdr and clear the tdre flag to 0. read tend flag in ssr no yes 1. 2. 3. initialize clear te bit to 0 in scr to continue transmitting serial data: after checking that the tdre flag is 1, indicating that data can be written, write data in tdr, then clear the tdre flag to 0. all data transmitted? tend = 1? 358 in transmitting serial data, the sci operates as follows. the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0 the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. after loading the data from tdr into tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output is selected, the sci outputs eight serial clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin in order from lsb (bit 0) to msb (bit 7). the sci checks the tdre flag when it outputs the msb (bit 7). if the tdre flag is 0, the sci loads data from tdr into tsr and begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, and after transmitting the msb, holds the txd pin in the msb state. if the teie bit in scr is set to 1, a transmit-end interrupt (tei) is requested at this time. after the end of serial transmission, the sck pin is held in a constant state. 359 figure 11-17 shows an example of sci transmit operation. figure 11-17 example of sci transmit operation transmit direction serial clock serial data tdre tend bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt handler writes data in tdr and clears tdre flag to 0 txi request txi request tei request 1 frame 360 receiving serial data: figure 11-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. when switching from asynchronous mode to synchronous mode, make sure that the orer, per, and fer flags are cleared to 0. if the fer or per flag is set to 1 the rdrf flag will not be set and both transmitting and receiving will be disabled. figure 11-18 sample flowchart for serial receiving (1) start receiving read rdrf flag in ssr read receive data from rdr, and clear rdrf flag to 0 in ssr read orer flag in ssr clear re bit to 0 in scr end error handling 1 4 5 no yes yes no yes 3 1. 2., 3. 4. 5. sci initialization: the receive data function of the rxd pin is selected automatically. receive error handling: if a receive error occurs, read the orer flag in ssr, then after executing the necessary error handling, clear the orer flag to 0. neither transmitting nor receiving can resume while the orer flag remains set to 1. sci status check and receive data read: read ssr, check that the rdrf flag is set to 1, then read receive data from rdr and clear the rdrf flag to 0. notification that the rdrf flag has changed from 0 to 1 can also be given by the rxi interrupt. to continue receiving serial data: check the rdrf flag, read rdr, and clear the rdrf flag to 0 before the msb (bit 7) of the current frame is received. initialize no rdrf = 1? orer = 1? finished receiving? 2 361 figure 11-18 sample flowchart for serial receiving (2) in receiving, the sci operates as follows. the sci synchronizes with serial clock input or output and initializes internally. receive data is stored in rsr in order from lsb to msb. after receiving the data, the sci checks that the rdrf flag is 0 so that receive data can be transferred from rsr to rdr. if this check passes, the rdrf flag is set to 1 and the received data is stored in rdr. if the check does not pass (receive error), the sci operates as indicated in table 11-11. after setting the rdrf flag to 1, if the rie bit is set to 1 in scr, the sci requests a receive- data-full interrupt (rxi). if the orer flag is set to 1 and the rie bit in scr is also set to 1, the sci requests a receive-error interrupt (eri). 3 end error handling overrun error handling clear orer flag to 0 in ssr 362 figure 11-19 shows an example of sci receive operation. figure 11-19 example of sci receive operation transmitting and receiving serial data simultaneously (synchronous mode): figure 11-20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. serial clock serial data bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi request receive direction rdrf orer rxi interrupt handler reads data in rdr and clears rdrf flag to 0 rxi request overrun error, eri request 1 frame 363 figure 11-20 sample flowchart for serial transmitting no yes no yes yes no yes no initialize start transmitting and receiving read tdre flag in ssr tdre = 1? write transmit data in tdr and clear tdre flag to 0 in ssr rdrf = 1? read rdrf flag in ssr read receive data from rdr and clear rdrf flag to 0 in ssr read orer flag in ssr orer = 1? end of transmitting and receiving? 1 2 5 3 1. 2. 3. 4. 5. sci initialization: the transmit data output function of the txd pin and receive data input function of the rxd pin are selected, enabling simultaneous transmitting and receiving. sci status check and transmit data write: read ssr, check that the tdre flag is 1, then write transmit data in tdr and clear the tdre flag to 0. error handling note: * when switching from transmitting or receiving to simultaneous transmitting and receiving, clear the te and re bits both to 0, then set the te and re bits both to 1. clear te and re bits to 0 in scr end notification that the tdre flag has changed from 0 to 1 can also be given by the txi interrupt. receive error handling: if a receive error occurs, read the orer flag in ssr, then after executing the neces- sary error handling, clear the orer flag to 0. neither transmitting nor receiving can resume while the orer flag remains set to 1. sci status check and receive data read: read ssr, check that the rdrf flag is 1, then read receive data from rdr and clear the rdrf flag to 0. notification that the rdrf flag has changed from 0 to 1 can also be given by the rxi interrupt. to continue transmitting and receiving serial data: check the rdrf flag, read rdr, and clear the rdrf flag to 0 before the msb (bit 7) of the current frame is received. also check that the tdre flag is (bit 7) of the current frame is received. also check that the tdre flag is set to 1, indicat- ing that data can be written, write data in tdr, then clear the tdre flag to 0 before the msb (bit 7) of the current frame is transmitted. when the dmac is activated by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre flag is checked and cleared automatically. 4 364 11.4 sci interrupts the sci has four interrupt request sources: tei (transmit-end interrupt), eri (receive-error interrupt), rxi (receive-data-full interrupt), and txi (transmit-data-empty interrupt). table 11-12 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, teie, and rie bits in scr. each interrupt request is sent separately to the interrupt controller. the txi interrupt is requested when the tdre flag is set to 1 in ssr. the tei interrupt is requested when the tend flag is set to 1 in ssr. the rxi interrupt is requested when the rdrf flag is set to 1 in ssr. the eri interrupt is requested when the orer, per, or fer flag is set to 1 in ssr. table 11-12 sci interrupt sources interrupt description priority eri receive error (orer, fer, or per) high rxi receive data register full (rdrf) txi transmit data register empty (tdre) tei transmit end (tend) low 365 11.5 usage notes note the following points when using the sci. tdr write and tdre flag: the tdre flag in ssr is a status flag indicating the loading of transmit data from tdr into tsr. the sci sets the tdre flag to 1 when it transfers data from tdr to tsr. data can be written into tdr regardless of the state of the tdre flag. if new data is written in tdr when the tdre flag is 0, the old data stored in tdr will be lost because this data has not yet been transferred to tsr. before writing transmit data in tdr, be sure to check that the tdre flag is set to 1. simultaneous multiple receive errors: table 11-13 indicates the state of ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs the rsr contents are not transferred to rdr, so receive data is lost. table 11-13 ssr status flags and transfer of receive data receive data transfer rdrf orer fer per rsr ? rdr receive errors 1100 overrun error 0010 o framing error 0001 o parity error 1110 overrun error + framing error 1101 overrun error + parity error 0011 o framing error + parity error 1111 overrun error + framing error + parity error notes: o : receive data is transferred from rsr to rdr. receive data is not transferred from rsr to rdr. ssr status flags 366 break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. in the break state the sci receiver continues to operate, so if the fer flag is cleared to 0 it will be set to 1 again. sending a break signal: when the te bit is cleared to 0 the txd pin becomes an i/o port, the level and direction (input or output) of which are determined by dr and ddr bits. this feature can be used to send a break signal. after the serial transmitter is initialized, the dr value substitutes for the mark state until the te bit is set to 1 (the txd pin function is not selected until the te bit is set to 1). the ddr and dr bits should therefore both be set to 1 beforehand. to send a break signal during serial transmission, clear the dr bit to 0, then clear the te bit to 0. when the te bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an output port outputting the value 0. receive error flags and transmitter operation (synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1 the sci will not start transmitting, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 when starting to transmit. note that clearing the re bit to 0 does not clear the receive error flags to 0. receive data sampling timing in asynchronous mode and receive margin: in asynchronous mode the sci operates on a base clock with 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 11-21. 367 figure 11-21 receive data sampling timing in asynchronous mode the receive margin in asynchronous mode can therefore be expressed as in equation (1). ...................(1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5 the receive margin is 46.875%, as given by equation (2). d = 0.5, f = 0 m = [0.5 ?1/(2 16)] 100% = 46.875%.................................................................................................(2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. internal base clock receive data (rxd) synchronization sampling timing data sampling timing 0 7 15 0 7 15 0 d 0 d 1 8 clocks 16 clocks start bit m = | (0.5 ? ) ?(l ?0.5) f ? (1 + f) | 100% 1 2n | d ?0.5 | n 368 restrictions in synchronous mode: when an external clock source is used in synchronous mode, after tdr is reset, wait at least 5 clock counts (5? before inputting the transmit clock. if the clock is input four states after the reset of tdr or earlier, an operation error may occur (figure 11-22). figure 11-22 transmission in synchronous mode (example) 369 tdre sck t d0 d1 d2 d3 d4 d5 d6 d7 note: when using an external clock, make sure t is 5 clock cycles or greater. 370 section 12 a/d converter 12.1 overview the h8/3032 series includes a 10-bit successive-approximations a/d converter with a selection of up to eight analog input channels. 12.1.1 features a/d converter features are listed below. 10-bit resolution eight input channels selectable analog conversion voltage range the analog voltage conversion range can be programmed by input of an analog reference voltage at the v ref pin. high-speed conversion conversion time: maximum 8.4 s per channel (with 16 mhz system clock) two conversion modes single mode: a/d conversion of one channel scan mode: continuous conversion on one to four channels four 16-bit data registers a/d conversion results are transferred for storage into data registers corresponding to the channels. sample-and-hold function a/d conversion can be externally triggered a/d interrupt requested at end of conversion at the end of a/d conversion, an a/d end interrupt (adi) can be requested. 371 12.1.2 block diagram figure 12-1 shows a block diagram of the a/d converter. figure 12-1 a/d converter block diagram module data bus bus interface on-chip data bus addra addrb addrc addrd adcsr adcr successive- approximations register 10-bit d/a av v av cc ref ss analog multi- plexer an an an an an an an an 0 1 2 3 4 5 6 7 sample-and- hold circuit comparator + control circuit adtrg ?8 ?16 adi legend adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d 372 12.1.3 input pins table 12-1 summarizes the a/d converter s input pins. the eight analog input pins are divided into two groups: group 0 (an 0 to an 3 ), and group 1 (an 4 to an 7 ). av cc and av ss are the power supply for the analog circuits in the a/d converter. v ref is the a/d conversion reference voltage. table 12-1 a/d converter pins abbrevi- pin name ation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage reference voltage pin v ref input analog reference voltage analog input pin 0 an 0 input group 0 analog inputs analog input pin 1 an 1 input analog input pin 2 an 2 input analog input pin 3 an 3 input analog input pin 4 an 4 input group 1 analog inputs analog input pin 5 an 5 input analog input pin 6 an 6 input analog input pin 7 an 7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion 373 12.1.4 register configuration table 12-2 summarizes the a/d converter s registers. table 12-2 a/d converter registers address * 1 name abbreviation r/w initial value h'ffe0 a/d data register a (high) addrah r h'00 h'ffe1 a/d data register a (low) addral r h'00 h'ffe2 a/d data register b (high) addrbh r h'00 h'ffe3 a/d data register b (low) addrbl r h'00 h'ffe4 a/d data register c (high) addrch r h'00 h'ffe5 a/d data register c (low) addrcl r h'00 h'ffe6 a/d data register d (high) addrdh r h'00 h'ffe7 a/d data register d (low) addrdl r h'00 h'ffe8 a/d control/status register adcsr r/(w) * 2 h'00 h'ffe9 a/d control register adcr r/w h'7e notes: 1. lower 16 bits of the address 2. only 0 can be written in bit 7, to clear the flag. 374 12.2 register descriptions 12.2.1 a/d data registers a to d (addra to addrd) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte of the a/d data register. the lower 2 bits are stored in the lower byte. bits 5 to 0 of an a/d data register are reserved bits that always read 0. table 12-3 indicates the pairings of analog input channels and a/d data registers. the cpu can always read and write the a/d data registers. the upper byte can be read directly, but the lower byte is read through a temporary register (temp). for details see section 12.3, cpu interface. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 12-3 analog input channels and a/d data registers analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd bit addrn initial value 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 0 r 4 0 r 2 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 0 r 5 0 r 3 0 r a/d conversion data 10-bit data giving an a/d conversion result reserved bits read/write (n = a to d) 375 12.2.2 a/d control/status register (adcsr) adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * note: only 0 can be written, to clear the flag. * a/d end flag indicates end of a/d conversion a/d interrupt enable enables and disables a/d end interrupts a/d start starts or stops a/d conversion scan mode selects single mode or scan mode clock select selects the a/d conversion time channel select 2 to 0 these bits select analog input channels 376 bit 7?/d end flag (adf): indicates the end of a/d conversion. bit 7 adf description 0 [clearing condition] (initial value) cleared by reading adf while adf = 1, then writing 0 in adf 1 [setting conditions] single mode: a/d conversion ends scan mode: a/d conversion ends in all selected channels bit 6?/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. bit 6 adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5?/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin. bit 5 adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends. scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. 377 bit 4?can mode (scan): selects single mode or scan mode. for further information on operation in these modes, see section 12.4, operation. clear the adst bit to 0 before switching the conversion mode. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?lock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3 cks description 0 conversion time = 266 states (maximum) (initial value) 1 conversion time = 134 states (maximum) bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits and the scan bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. group selection channel selection description ch2 ch1 ch0 single mode scan mode 000 an 0 (initial value) an 0 1an 1 an 0 , an 1 10 an 2 an 0 to an 2 1an 3 an 0 to an 3 100 an 4 an 4 1an 5 an 4 , an 5 10 an 6 an 4 to an 6 1an 7 an 4 to an 7 378 12.2.3 a/d control register (adcr) adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion. adcr is initialized to h'7f by a reset and in standby mode. bit 7?rigger enable (trge): enables or disables external triggering of a/d conversion. bit 7 trge description 0 a/d conversion cannot be externally triggered (initial value) 1 a/d conversion starts at the falling edge of the external trigger signal ( adtrg ) bits 6 to 0?eserved: read-only bits, always read as 1. bit initial value read/write 7 trge 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 trigger enable enables or disables external triggering of a/d conversion reserved bits 379 12.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, although the upper byte can be be accessed directly by the cpu, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 12-2 shows the data flow for access to an a/d data register. figure 12-2 a/d data register access operation (reading h'aa40) upper-byte read bus interface module data bus cpu (h'aa) addrnh (h'aa) addrnl (h'40) lower-byte read bus interface module data bus cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) 380 12.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 12.4.1 single mode (scan = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 12-3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 381 figure 12-3 example of a/d converter operation (single mode, channel 1 selected) adie adst adf state of channel 0 (an ) set set set clear clear idle idle idle idle a/d conversion a/d conversion idle read conversion result a/d conversion result read conversion result a/d conversion result 2 note: vertical arrows ( ) indicate instructions executed by software. 0 1 2 3 a/d conversion starts * * * * * 2 1 1 * addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) idle 382 12.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0, an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an 0 to an 2 ) are selected in scan mode are described next. figure 12-4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred into addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ). 383 figure 12-4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) adst adf state of channel 0 (an ) 0 1 2 3 continuous a/d conversion set clear * 1 clear * 1 idle a/d conversion idle idle idle a/d conversion idle a/d conversion idle a/d conversion idle a/d conversion idle idle transfer a/d conversion result a/d conversion result a/d conversion result a/d conversion result 1. 2. a/d conversion time notes: * 2 1 4 2 5 * 1 3 1 4 2 3 addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) vertical arrows ( ) indicate instructions executed by software. data currently being converted is ignored. 384 12.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 12-5 shows the a/d conversion timing. table 12-4 indicates the a/d conversion time. as indicated in figure 12-5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 12-4. in scan mode, the values given in table 12-4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. figure 12-5 a/d conversion timing address bus write signal input sampling timing adf (1) (2) t d t spl t conv legend (1): (2): t : t : t : d spl conv adcsr write cycle adcsr address synchronization delay input sampling time a/d conversion time 385 table 12-4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max synchronization delay t d 10?76 ? input sampling time t spl ?040 a/d conversion time t conv 259 266 131 134 note: values in the table are numbers of states. 12.4.4 external trigger input timing a/d conversion can be externally triggered. when the trge bit is set to 1 in adcr, external trigger input is enabled at the adtrg pin. a high-to-low transition at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit had been set to 1 by software. figure 12-6 shows the timing. figure 12-6 external trigger input timing adtrg internal trigger signal adst a/d conversion 386 12.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 12.6 usage notes when using the a/d converter, note the following points: analog input voltage range: during a/d conversion, the voltages input to the analog input pins an n should be in the range av ss an n v ref . (n = 0 to 7) av cc and av ss input voltages: av ss should have the following values: av ss = v ss . if the a/d converter is not used, the values should be av cc = v cc and av ss = v ss . v ref input range: the analog reference voltage input at the v ref pin should be in the range v ref av cc . if the a/d converter is not used, the value should be v ref = v cc . 387 388 section 13 ram 13.1 overview the h8/3032 has 2 kbytes of on-chip static ram, the h8/3031 has 1 kbyte, and the h8/3030 has 512 bytes. the ram is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, making the ram suitable for rapid data transfer. the h8/3032 on-chip ram is assigned to addresses h'ff710 to h'fff0f in modes 1 and 3, and addresses h'f7 10 to h'ff0f in mode 2. the h8/3031 on-chip ram is assigned to addresses h'ffb10 to h'fff0f in modes 1 and 3, and addresses h'fb10 to h'ff0f in mode 2. the h8/3030 on-chip ram is assigned to addresses h'ffd10 to h'fff0f in modes 1 and 3, and addresses h'fd10 to h'ff0f in mode 2. the ram enable bit (rame) in the system control register (syscr) can enable or disable the on-chip ram. 13.1.1 block diagram figure 13-1 shows a block diagram of the on-chip ram. figure 13-1 ram block diagram (h8/3031 in mode 2) h'fb10 h'fb12 * h'ff0e * h'fb11 h'fb13 * * h'ff0f * on-chip data bus (upper 8 bits) on-chip data bus (lower 8 bits) bus interface on-chip ram even addresses odd addresses note: lower 16 bits of the address * 389 13.1.2 register configuration the on-chip ram is controlled by the system control register (syscr). table 13-1 gives the address and initial value of syscr. table 13-1 ram control register address * name abbreviation r/w initial value h'fff2 system control register syscr r/w h'0b note: * lower 16 bits of the address 390 13.2 system control register (syscr) one function of syscr is to enable or disable access to the on-chip ram. the on-chip ram is enabled or disabled by the rame bit in syscr. for details about the other bits, see section 3.3, system control register. b it 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized at the rising edge of the input at the res pin. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 2 nmieg 0 r/w 1 1 0 rame 1 r/w software standby standby timer select 2 to 0 user bit enable nmi edge select reserved bit ram enable bit enables or disables on-chip ram 391 13.3 operation 13.3.1 mode 1 when the rame bit is set to 1 in mode 1, accesses to addresses h'ff710 to h'fff0f of the h8/3032, to addresses h'ffb10 to h'fff0f of the h8/3031, and to addresses h'ffd10 to h'fff0f of the h8/3030 are directed to the on-chip ram space. when the rame bit is cleared to 0, accesses to such addresses are directed to the off-chip address space. 13.3.2 modes 2 and 3 when the rame bit is set to 1 in modes 2 and 3, accesses to addresses h'f710 to h'ff0f of the h8/3032, to addresses h'fb10 to h'ff0f of the h8/3031, and to addresses h'fd10 to h'ff0f of the h8/3030 are directed to the on-chip ram space. when the rame bit is cleared to 0, read accesses to such addresses always return h'ff and write accesses are ignored. note that these addresses represent the lower 16 bits of the address. 392 393 section 14 rom 14.1 overview the h8/3030 has 16 kbytes of on-chip rom, the h8/3031 has 32 kbytes, and the h8/3032 has 64 kbytes. the rom is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, enabling rapid data transfer. the prom version of the h8/3032 can be set to prom mode and programmed with a general- purpose prom programmer. 14.1.1 block diagram figure 14-1 shows a block diagram of the rom. figure 14-1 rom block diagram (h8/3032) h'0000 h'0002 h'fffe h'0001 h'0003 h'ffff on-chip data bus (upper 8 bits) on-chip data bus (lower 8 bits) on-chip rom even addresses odd addresses 394 14.2 prom mode 14.2.1 prom mode setting in prom mode, the h8/3032 version with on-chip prom suspends its microcontroller functions, enabling the on-chip prom to be programmed. the programming method is the same as for the hn27c101, except that page programming is not supported. table 14-1 indicates how to select prom mode. table 14-1 selecting prom mode pins setting two mode pins (md 1 and md 0 ) low stby pin p5 1 and p5 0 high 14.2.2 socket adapter and memory map the prom is programmed using a general-purpose prom programmer with a socket adapter to convert to 32 pins. table 14-2 lists the socket adapter for each package option. figure 14-2 shows the pin assignments of the socket adapter. figure 14-3 shows a memory map in prom mode. table 14-2 socket adapter microcontroller package socket adapter h8/3032 80-pin qfp (fp-80a) hs3032esh01h 80-pin tqfp (tfp-80c) hs3032esn01h the size of the h8/3032 prom is 64 kbytes. figure 14-3 shows a memory map in prom mode. h'ff data should be specified for unused address areas in the on-chip prom. when programming the h8/3032 with a prom programmer, set the address range to h'0000 to h'ffff and specify h'ff data for addresses h'10000 and up. if h'10000 and higher addresses are programmed by mistake, it may become impossible to program or verify the prom. attempts to program in page-programming mode may have the same result. 395 figure 14-2 socket adapter pin assignments h8/3032 fp-80a, tfp-80c 57 49 43 69 70 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 68 67 21 53 44 45 47 58 12 30 50 pin reso nmi p6 0 p8 0 p8 1 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p5 0 p5 1 av cc v ref v cc v cc md 0 md 1 stby av ss v ss v ss v ss pin v ea ea ea pgm eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce v v prom socket hn27c101 (32 pins) 1 26 3 2 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 legend v : eo to eo : ea to ea : oe: ce: pgm: programming voltage (12.5 v) data input/output address input output enable chip enable program pp cc ss pp note: pins not shown in this diagram should be left open. 9 15 16 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 10 11 12 13 14 7 16 0 0 396 figure 14-3 h8/3032 memory map in prom mode on-chip prom missing area h'0000 h'ffff h'0000 h'ffff h'1ffff address in mcu mode address in prom mode * note: if read in prom mode, this area returns h'ff output data. * h'1ffff 397 14.3 programming table 14-3 indicates how to select the program, verify, and other modes in prom mode. table 14-3 mode selection in prom mode pins mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 program l h l v pp v cc data input address input verify l l h v pp v cc data output address input program inhibited l l l v pp v cc high impedance address input lhh hl l hhh legend l: low voltage level h: high voltage level v pp :v pp voltage level v cc :v cc voltage level read/write specifications are the same as for the standard hn27c101 eprom, except that page programming is not supported. do not select page programming mode. a prom programmer that supports only page-programming mode cannot be used. when selecting a prom programmer, check that it supports a byte-at-a-time high-speed programming mode. be sure to set the address range to h'0000 to h'ffff. 14.3.1 programming and verification an efficient, high-speed programming procedure can be used to program and verify prom data. this procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. unused address areas contain h'ff data. figure 14-4 shows the basic high-speed programming flowchart. tables 14-4 and 14-5 list the electrical characteristics of the chip during programming. figure 14-5 shows a timing chart. 398 figure 14-4 high-speed programming flowchart start set programming/verification mode v = 6.0 v ?.25 v, v = 12.5 v ?.3 v cc pp address = 0 ? pw verification ok? program with t = 0.2n ms opw last address? set read mode v = 5.0 v ?.25 v, v = v cc pp cc all addresses read? end fail n 25 < address + 1 address ? no yes no yes no no program with t = 0.2 ms ?% n = 0 n + 1 n yes yes 399 table 14-4 dc characteristics ?reliminary (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25? 5?) item symbol min typ max unit test conditions input high eo 7 to eo 0 , v ih 2.4 v cc + 0.3 v voltage ea 16 to ea 0 , oe , ce , pgm input low eo 7 to eo 0 , v il C0.3 0.8 v voltage ea 16 to ea 0 , oe , ce , pgm output high eo 7 to eo 0 v oh 2.4 v i oh = C200 a voltage output low eo 7 to eo 0 v ol 0.45 v i ol = 1.6 ma voltage input leakage eo 7 to eo 0 , |i li | 2 a v in = 5.25 v/0.5 v current ea 16 to ea 0 , oe , ce , pgm v cc current i cc 40 ma v pp current i pp 40 ma 400 table 14-5 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25? 5?) item symbol min typ max unit test conditions address setup time t as 2 s figure 14-5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite t opw * 3 0.19 5.25 ms programming v cc setup time t vcs 2 s ce setup time t ces 2 s data output delay time t oe 0 150 ns notes: 1. input pulse level: 0.8 v to 2.2 v input rise time and fall time 20 ns timing reference levels: 1.0 v and 2.0 v for input; 0.8 v and 2.0 v for output 2. t df is defined at the point where the output is in the open state and the output level cannot be read. 3. t opw is defined by the value given in the flowchart. 401 figure 14-5 prom program/verify timing address data v pp v cc ce pgm oe v pp v cc v cc v cc program verify input data output data t as t ds t vps t vcs t ces t pw t opw * t dh t oes t oe t df t ah note: t is defined by the value given in the flowchart. * opw +1 402 14.3.2 programming precautions program with the specified voltages and timing. the programming voltage (v pp ) in prom mode is 12.5 v. applied voltages in excess of the rated values can permanently destroy the chip. be particularly careful about the prom programmer s overshoot characteristics. if the prom programmer is set to hitachi hn27c101 specifications, v pp will be 12.5 v. before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the chip can result if the index marks on the prom programmer, socket adapter, and chip are not correctly aligned. don t touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. select the programming mode carefully. the chip cannot be programmed in page programming mode. the h8/3032 prom size is 64 kbytes. set the address range to h'0000 to h'ffff. when programming, assign h'ff data to the unused address area (h'10000 to h'1ffff). 403 14.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150?, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 14-6 shows the recommended screening procedure. figure 14-6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. install program chip and verify programmed data bake chip for 24 to 48 hours at 125? to 150? with power off read and check program 404 section 15 clock pulse generator 15.1 overview the h8/3032 series has a built-in clock pulse generator (cpg) that generates the system clock (? and other internal clock signals (?2 to ?4096). the clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, and prescalers. 15.1.1 block diagram figure 15-1 shows a block diagram of the clock pulse generator. figure 15-1 block diagram of clock pulse generator xtal extal cpg ?2 to ?4096 oscillator duty adjustment circuit prescalers 405 15.2 oscillator circuit clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 15.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as in the example in figure 15-2. the damping resistance rd should be selected according to table 15-1. an at-cut parallel- resonance crystal should be used. figure 15-2 connection of crystal resonator (example) table 15-1 damping resistance value frequency (mhz) 2 4 8 10 12 16 rd ( ) 1 k 500 200 0 0 0 crystal resonator: figure 15-3 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 15-2. figure 15-3 crystal resonator equivalent circuit extal xtal c l1 c l2 c = c = 10 pf to 22 pf l1 l2 rd xtal lrs c l c o extal at-cut parallel-resonance type 406 table 15-2 crystal resonator parameters frequency (mhz) 248101216 rs max ( ) 500 120 80 70 60 50 co (pf) 7 pf max use a crystal resonator with a frequency equal to the system clock frequency (?. notes on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 15-4. when the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. figure 15-4 example of incorrect board design xtal extal c l2 c l1 h8/3032 series avoid signal a signal b 407 15.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 15-5. in example b, the clock should be held high in standby mode. if the xtal pin is left open, the stray capacitance should not exceed 10 pf. figure 15-5 external clock input (examples) extal xtal extal xtal 74hc04 external clock input open external clock input a. xtal pin left open b. complementary clock input at xtal pin 408 external clock: the external clock frequency should be equal to the system clock frequency (?. table 15-3 and figure 15-6 indicate the clock timing. table 15-3 clock timing v cc = 2.7 v to 5.5 v v cc = 5.0 v 10% item symbol min max min max unit test conditions external clock rise t exr 10 5 ns figure 15-16 time external clock fall t exf ?0 5 ns time external clock 30 70 30 70 % ? 3 5 mhz figure input duty (a/t cyc ) 40 60 40 60 % ? < 5 mhz 15-6 ? clock duty 40 60 40 60 % figure 15-6 (b/t cyc ) figure 15-6 external clock input timing t cyc a extal t exr t exf v cc 0.5 t cyc b v cc 0.5 409 15.3 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (?. 15.4 prescalers the prescalers divide the system clock (? to generate internal clocks (?2 to ?4096). 410 section 16 power-down state 16.1 overview the h8/3032 series has a power-down state that greatly reduces power consumption by halting cpu functions. the power-down state includes the following three modes: sleep mode software standby mode hardware standby mode table 16-1 indicates the methods of entering and exiting these power-down modes and the status of the cpu and on-chip supporting modules in each mode. table 16-1 power-down state state entering cpu supporting i/o exiting mode conditions clock cpu registers functions ram ports conditions sleep sleep instruc- active halted held active held held interrupt mode tion executed res while ssby = 0 ? stby in syscr software sleep instruc- halted halted held halted held held ? nmi standby tion executed and ? irq 0 to irq 2 mode while ssby = 1 reset ? res in syscr ? stby hardware low input at halted halted undeter halted held * high stby standby stby pin mined and impedance ? res mode reset note: * the rame bit must be cleared to 0 in syscr before the transition from the program execution state to hardware standby mode. legend syscr: system control register ssby: software standby bit 411 16.2 register configuration the h8/3032 series?system control register (syscr) controls the power-down state. table 16-2 summarizes this register. table 16-2 control register address * name abbreviation r/w initial value h'fff2 system control register syscr r/w h'0b note: * lower 16 bits of the address. 16.2.1 system control register (syscr) syscr is an 8-bit readable/writable register. bit 7 (ssby) and bits 6 to 4 (sts2 to sts0) control the power-down state. for information on the other syscr bits, see section 3.3, system control register. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 1 software standby enables transition to software standby mode ram enable standby timer select 2 to 0 these bits select the waiting time at exit from software standby mode user bit enable nmi edge select reserved bit 412 bit 7?oftware standby (ssby): enables transition to software standby mode. when software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?tandby timer select (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. if the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 8 ms. see table 16-3. if an external clock is used, any setting is permitted. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 000w aiting time = 8192 states (initial value) 1 waiting time = 16384 states 1 0 waiting time = 32768 states 1 waiting time = 65536 states 1 0 waiting time = 131072 states 1 illegal setting 413 16.3 sleep mode 16.3.1 transition to sleep mode when the ssby bit is cleared to 0 in the system control register (syscr), execution of the sleep instruction causes a transition from the program execution state to sleep mode. immediately after executing the sleep instruction the cpu halts, but the contents of its internal registers are retained. the on-chip supporting modules do not halt in sleep mode. 16.3.2 exit from sleep mode sleep mode is exited by an interrupt, or by input at the res or stby pin. exit by interrupt: an interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. sleep mode is not exited by an nmi interrupt if masked in the cpu. exit by res input: low input at the res pin exits from sleep mode to the reset state. exit by stby input: low input at the stby pin exits from sleep mode to hardware standby mode. 414 16.4 software standby mode 16.4.1 transition to software standby mode to enter software standby mode, execute the sleep instruction while the ssby bit is set to 1 in syscr. in software standby mode, current dissipation is reduced to an extremely low level because the cpu, clock, and on-chip supporting modules all halt. the on-chip supporting modules are reset. as long as the specified voltage is supplied, however, cpu register contents and on-chip ram data are retained. the settings of the i/o ports are also held. 16.4.2 exit from software standby mode software standby mode can be exited by input of an external interrupt at the nmi, irq 0 , irq 1 , or irq 2 pin, or by input at the res or stby pin. exit by interrupt: when an nmi, irq 0 , irq 1 , or irq 2 interrupt request signal is received, the clock oscillator begins operating. after the oscillator settling time selected by bits sts2 to sts0 in syscr, stable clock signals are supplied to the entire h8/3032 series chip, software standby mode ends, and interrupt exception handling begins. software standby mode is not exited if the interrupt enable bits of interrupts irq 0 , irq 1 , and irq 2 are cleared to 0, or if these interrupts are masked in the cpu. exit by res input: when the res input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire h8/3032 series chip. the res signal must be held low long enough for the clock oscillator to stabilize. when res goes high, the cpu starts reset exception handling. exit by stby input: low input at the stby pin causes a transition to hardware standby mode. 415 16.4.3 selection of waiting time for exit from software standby mode bits sts2 to sts0 in syscr should be set as follows. crystal resonator: set sts2 to sts0 so that the waiting time (for the clock to stabilize) is at least 8 ms. table 16-3 indicates the waiting times that are selected by sts2 to sts0 settings at various system clock frequencies. external clock: any value may be set in the clock-halving version. normally the minimum value (sts2 = sts1 = sts0 = 1) is recommended. in the 1:1 clock version, any value other than the minimum value may be set. table 16-3 clock frequency and waiting time for clock to settle waiting sts2 sts1 sts0 time 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms states 0 0 1 16384 1.0 1.3 1.6 2.0 2.7 4.1 8.2 states 0 1 0 32768 2.0 2.7 3.3 4.1 5.5 8.2 16.4 states 0 1 1 65536 4.1 5.5 6.6 8.2 10.9 16.4 32.8 states 1 0 131072 8.2 10.9 13.1 16.4 21.8 32.8 65.5 states 1 1 illegal setting : recommended setting note: * this setting cannot be used in the 1:1 clock version. 416 16.4.4 sample application of software standby mode figure 16-1 shows an example in which software standby mode is entered at the fall of nmi and exited at the rise of nmi. with the nmi edge select bit (nmieg) cleared to 0 in syscr (selecting the falling edge), an nmi interrupt occurs. next the nmieg bit is set to 1 (selecting the rising edge) and the ssby bit is set to 1; then the sleep instruction is executed to enter software standby mode. software standby mode is exited at the next rising edge of the nmi signal . figure 16-1 nmi timing for software standby mode (example) 16.4.5 note the i/o ports retain their existing states in software standby mode. if a port is in the high output state, its output current is not reduced. nmi nmieg ssby nmi interrupt handler nmieg = 1 ssby = 1 software standby mode (power- down state) oscillator settling time (t osc2 ) sleep instruction nmi exception handling clock oscillator 417 16.5 hardware standby mode 16.5.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting all functions of the cpu and on-chip supporting modules. all modules are reset except the on-chip ram. as long as the specified voltage is supplied, on-chip ram data is retained. i/o ports are placed in the high-impedance state. clear the rame bit to 0 in syscr before stby goes low to retain on-chip ram data. the inputs at the mode pins (md1 to md0) should not be changed during hardware standby mode. 16.5.2 exit from hardware standby mode hardware standby mode is exited by inputs at the stby and res pins. while res is low, when stby goes high, the clock oscillator starts running. res should be held low long enough for the clock oscillator to settle. when res goes high, reset exception handling begins, followed by a transition to the program execution state. 16.5.3 timing for hardware standby mode figure 16-2 shows the timing relationships for hardware standby mode. to enter hardware standby mode, first drive res low, then drive stby low. to exit hardware standby mode, first drive stby high, wait for the clock to settle, then bring res from low to high. figure 16-2 hardware standby mode timing res stby clock oscillator oscillator settling time reset exception handling 418 section 17 electrical characteristics 17.1 absolute maximum ratings table 17-1 lists the absolute maximum ratings. table 17-1 absolute maximum ratings ?reliminary item symbol value unit power supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.5 v input voltage (except port 7) v in ?.3 to v cc +0.3 v input voltage (port 7) v in ?.3 to av cc +0.3 v reference voltage v ref ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr regular specifications: ?0 to +75 ? wide-range specifications: ?0 to +85 ? storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 419 17.2 electrical characteristics 17.2.1 dc characteristics table 17-2 lists the dc characteristics. table 17-3 lists the permissible output currents. table 17-2 dc characteristics conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v*, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions port a, v t 1.0 v p8 0 to p8 2 ,v t + v cc 0.7 v pb 0 to pb 3 v t + e v t e 0.4 ? ? v input high res , stby , v ih v cc C 0.7 v cc + 0.3 v voltage nmi, md 1 , md 0 extal v cc 0.7 ? v cc + 0.3 v port 7 2.0 ? av cc + 0.3 v ports 1, 2, 3, 2.0 ? v cc + 0.3 v 5, 6, 9, p8 3 , pb 4 to pb 7 input low res , stby , v il C0.3 0.5 v voltage md 1 , md 0 nmi, extal, C0.3 0.8 v ports 1, 2, 3, 5, 6, 7, 9, p8 3 , pb 4 to pb 7 all output pins v oh v cc C 0.5 v i oh = C200 a 3.5 v i oh = C1 ma note: * if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . output high voltage schmitt trigger input voltages 420 table 17-2 dc characteristics (cont) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v *1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except reso ) ports 1, 2, 5 1.0 v i ol = 10 ma and b reso 0.4 v i ol = 2.6 ma input leakage stby , nmi, |i in | 1.0 a v in = 0.5 to current res ,v cc C 0.5 v md 1 , md 0 port 7 1.0 a v in = 0.5 to av cc C 0.5 v ports 1, 2, |i ts1 | 1.0 a v in = 0.5 to 3, 4, 5, 6, v cc C 0.5 v 8 to b reso 10.0 a v in = 0.5 to v cc C 0.5 v input pull-up ports 2 and 5 Ci p 50 300 a v in = 0 v current input nmi c in 50pfv in = 0 v capacitance all input pins 15 f = 1 mhz except nmi t a = 25c current normal i cc 45 60 ma f = 16 mhz dissipation * 2 operation sleep mode 32 45 ma f = 16 mhz standby 0.01 5.0 a t a 50c mode * 3 20.0 a 50? < t a notes: 1. if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 4.5 v, v ihmin = v cc 0.9, and v ilmax = 0.3 v. three-state leakage current (off state) 421 table 17-2 dc characteristics (cont) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v *1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions analog power during a/d ai cc 1.2 2.0 ma supply current conversion idle 0.01 5.0 a reference during a/d ai cc 0.3 0.6 ma v ref = 5.0 v current conversion idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram < v cc < 4.5 v, v ihmin = v cc 0.9, and v ilmax = 0.3 v. conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v*, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt port a, v t v cc 0.2 ? ? v v t + ??v cc 0.7 v v t + e v t e v cc 0.07 ? ? v input high res , stby , v ih v cc 0.9 ? v cc + 0.3 v voltage nmi, md 1 , md 0 extal v cc 0.7 ? v cc + 0.3 v port 7 v cc 0.7 ? av cc + 0.3 v ports 1, 2, 3, v cc 0.7 ? v cc + 0.3 v 5, 6, 9, p8 3 , pb 4 to pb 7 note: * if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . schmitt port a, trigger input p8 0 to p8 2 , voltages pb 0 to pb 3 422 table 17-2 dc characteristics (cont) conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v*, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions input low res , stby , v il C0.3 v cc 0.1 v voltage md 1 , md 0 e0.3 ? v cc 0.2 v v cc < 4.0 v 0.8 v v cc = 4.0 to 5.5 v output high all output pins v oh v cc e 0.5 ? ? v i oh = e200 a voltage v cc e 1.0 ? ? v i oh = e1 ma output low all output pins v ol ? ? 0.4 v i ol = 1.6 ma voltage (except reso ) ports 1, 2, 5 1.0 v v cc 4 v, and b i ol = 5 ma, 4 v v cc 5.5 v, i ol = 10 ma reso 0.4 v i ol = 1.6 ma input leakage stby , nmi, |i in | 1.0 a v in = 0.5 to current res , v cc C 0.5 v md 1 , md 0 port 7 1.0 a v in = 0.5 to av cc C 0.5 v three-state ports 1, 2, 3, |i ts1 | 1.0 a v in = 0.5 to leakage 5, 6, 8 to b v cc C 0.5 v current reso 10.0 a v in = 0.5 to (off state) v cc C 0.5 v input pull-up ports 2 Ci p 10 300 a v cc = 2.7 v to current and 5 5.5 v, v in = 0 v note: * if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . nmi, extal, ports 1, 2, 3, 5, 6, 7, 9, p8 3 , pb 4 to pb 7 423 table 17-2 dc characteristics (cont) conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v *1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions nmi c in 50pf all input pins 15 except nmi current normal i cc * 4 12 31.8 ma f = 8 mhz dissipation * 2 operation (3.0 v) (5.5 v) sleep mode 8 23.0 ma f = 8 mhz (3.0 v) (5.5 v) 0.01 5.0 a t a 50c 20.0 a 50c < t a ai cc 1.0 2.0 ma av cc = 3.0 v 1.2 ma av cc = 5.0 v idle 0.01 5.0 a ai cc 0.2 0.4 ma v ref = 3.0 v 0.3 ma v ref = 5.0 v idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc C 0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 2.7 v, v ihmin = v cc 0.9, and v ilmax = 0.3 v. 4. i cc depends on v cc and f as follows: i ccmax = 1.0 (ma) + 0.7 (ma/mhz v) v cc f [normal mode] i ccmax = 1.0 (ma) + 0.5 (ma/mhz v) v cc f [sleep mode] input capacitance v in = 0 v f = 1 mhz t a = 25?c analog power during a/d supply current conversion reference during a/d current conversion standby mode * 3 424 table 17-2 dc characteristics (cont) conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v*, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions v t v cc 0.2 ? ? v v t + ??v cc 0.7 v v t + e v t e v cc 0.07 ? ? v input high res , stby , v ih v cc 0.9 ? v cc + 0.3 v voltage nmi, md 1 , md 0 extal v cc 0.7 ? v cc + 0.3 v port 7 v cc 0.7 ? av cc + 0.3 v ports 1, 2, 3, v cc 0.7 ? v cc + 0.3 v 5, 6, 9, p8 3 , pb 4 to pb 7 input low res , stby , v il C0.3 v cc 0.1 v voltage md 1 , md 0 nmi, extal, e0.3 ? v cc 0.2 v v cc < 4.0 v ports 1, 2, 3, 5, 6, 7, 9, p8 3 , 0.8 v v cc = pb 4 to pb 7 4.0 to 5.5 v output high all output pins v oh v cc e 0.5 ? ? v i oh = e200 a voltage v cc e 1.0 ? ? v i oh = e1 ma note: * if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 425 schmitt port a, trigger input p8 0 to p8 2 , voltages pb 0 to pb 3 table 17-2 dc characteristics (cont) conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v*, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except reso ) ports 1, 2, 5 1.0 v v cc 4 v and b i ol = 5 ma, 4 v < v cc 5.5 v i ol = 10 ma reso 0.4 v i ol = 1.6 ma input leakage stby , nmi, |i in | 1.0 a v in = 0.5 to current res , v cc C 0.5 v md 1 , md 0 port 7 1.0 a v in = 0.5 to av cc C 0.5 v three-state ports 1, 2, 3, |i ts1 | 1.0 a v in = 0.5 to leakage 5, 6, 8 to b v cc C 0.5 v current reso 10.0 a v in = 0.5 to (off state) v cc C 0.5 v input pull-up pors 2 Ci p 10 300 a v cc = 3.0 v to current and 5 5.5 v, v in = 0 v note: * if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 426 table 17-2 dc characteristics (cont) conditions: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v *1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions nmi c in 50pf all input pins 15 except nmi current normal i cc * 4 15 39.5 ma f = 10 mhz dissipation * 2 operation (3.0 v) (5.5 v) sleep mode 10 28.5 ma f = 10 mhz (3.0 v) (5.5 v) 0.01 5.0 a t a 50c 20.0 a 50c < t a ai cc 1.0 2.0 ma av cc = 3.0 v 1.2 ma av cc = 5.0 v idle 0.01 5.0 a ai cc 0.2 0.4 ma v ref = 3.0 v 0.3 ma v ref = 5.0 v idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d converter is not used, do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc C 0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ihmin = v cc 0.9, and v ilmax = 0.3 v. 4. i cc depends on v cc and f as follows: i ccmax = 1.0 (ma) + 0.7 (ma/mhz v) v cc f [normal mode] i ccmax = 1.0 (ma) + 0.5 (ma/mhz v) v cc f [sleep mode] 427 input capacitance v in = 0 v f = 1 mhz t a = 25?c analog power during a/d supply current conversion reference during a/d current conversion standby mode * 3 table 17-3 permissible output currents (1) conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit ports 1, 2, 5 and b i ol 10ma other output pins 2.0 ma permissible output total of 28 pins including s i ol ??80ma low current (total) ports 1, 2, 5 and b total of all output pins, ? ? 120 ma including the above permissible output all output pins i oh ? ? 2.0 ma high current (per pin) permissible output total of all output pins s i oh ??40ma high current (total) notes: 1. to protect chip reliability, do not exceed the output current values in table 17-3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as shown in figures 17-1 and 17-2. permissible output low current (per pin) 428 figure 17-1 darlington pair drive circuit (example) figure 17-2 led drive circuit (example) h8/3032 series ports 5 and b led 600 w h8/3032 series port 2 k w darlington pair 429 17.2.2 ac characteristics bus timing parameters are listed in table 17-4. control signal timing parameters are listed in table 17-5. timing parameters of the on-chip supporting modules are listed in table 17-6. table 17-4 bus timing (1) condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions clock cycle time t cyc 125 500 100 500 62.5 500 ns figure 17-4, clock low pulse width t cl 40 40 20 figure 17-5 clock high pulse width t ch 40 30 20 clock rise time t cr ?0 15?0 clock fall time t cf ?0 15?0 address delay time t ad ?0 50?0 address hold time t ah 25 20 10 address strobe delay t asd ?0 40?0 time write strobe delay time t wsd ?0 50?0 strobe delay time t sd ?0 50?0 write data strobe pulse t wsw1 * 85 60 35 width 1 write data strobe pulse t wsw2 * 150?10?5 width 2 address setup time 1 t as1 20 15 10 address setup time 2 t as2 80 65 40 read data setup time t rds 50 35 20 read data hold time t rdh 0 0 0 430 table 17-4 bus timing (cont) condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions write data delay time t wdd 75 75 60 ns figure 17-4, write data setup time 1 t wds1 90 40 15 figure 17-5 write data setup time 2 t wds2 5 ?0 5 write data hold time t wdh 25 20 20 read data access t acc1 * ?10?00?5 time 1 read data access t acc2 * 230 200 115 time 2 read data access t acc3 * ?5 50?5 time 3 read data access t acc4 * 160 150 85 time 4 precharge time t pch * 85 60 40 wait setup time t wts 40 40 25 ns figure 17-6 wait hold time t wth 10 10 5 note is on next page. 431 note: at 8 mhz, the times below depend as indicated on the clock cycle time. t acc1 = 1.5 t cyc e 78 (ns) t wsw1 = 1.0 t cyc e 40 (ns) t acc2 = 2.5 t cyc e 83 (ns) t wsw2 = 1.5 t cyc e 38 (ns) t acc3 = 1.0 t cyc e 70 (ns) t pch = 1.0 t cyc e 40 (ns) t acc4 = 2.0 t cyc e 90 (ns) at 10 mhz, the times below depend as indicated on the clock cycle time. t acc1 = 1.5 t cyc e 50 (ns) t wsw1 = 1.0 t cyc e 40 (ns) t acc2 = 2.5 t cyc e 50 (ns) t wsw2 = 1.5 t cyc e 40 (ns) t acc3 = 1.0 t cyc e 50 (ns) t pch = 1.0 t cyc e 40 (ns) t acc4 = 2.0 t cyc e 50 (ns) at 16 mhz, the times below depend as indicated on the clock cycle time. t acc1 = 1.5 t cyc e 39 (ns) t wsw1 = 1.0 t cyc e 28 (ns) t acc2 = 2.5 t cyc e 41 (ns) t wsw2 = 1.5 t cyc e 28 (ns) t acc3 = 1.0 t cyc e 38 (ns) t pch = 1.0 t cyc e 23 (ns) t acc4 = 2.0 t cyc e 40 (ns) 432 table 17-5 control signal timing condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions res setup time t ress 200 200 200 ns figure 17-7 res pulse width t resw 10 10 10 t cyc reso output delay t resd 100 100 100 ns figure 17-8 time reso output pulse t resow 132 132 132 t cyc width nmi setup time t nmis 200 200 150 ns figure 17-9 (nmi, irq 4 to irq 0 ) nmi hold time t nmih 10 10 10 (nmi, irq 4 to irq 0 ) interrupt pulse width t nmiw 200 200 200 (nmi, irq 4 to irq 0 when exiting software standby mode) clock oscillator settling t osc1 20 20 20 ms figure 17-10 time at reset (crystal) clock oscillator settling t osc2 8 8 8 figure 16-1 time in software standby (crystal) 433 table 17-6 timing of on-chip supporting modules condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions itu timer output t tocd 100 100 100 ns figure 17-12 delay time timer input t tics 50 50 50 setup time timer clock t tcks 50 50 50 figure 17-13 input setup time single t tckwh 1.5 1.5 1.5 t cyc edge both t tckwl 2.5 2.5 2.5 edges sci asyn- t scyc 4 4 4 figure 17-14 chronous syn- t scyc 6 6 6 chronous input clock rise t sckr 1.5 1.5 1.5 time input clock fall t sckf 1.5 1.5 1.5 time input clock t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc pulse width input clock cycle timer clock pulse width 434 table 17-6 timing of on-chip supporting modules (cont) condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions sci transmit data t txd 100 100 100 ns figure 17-15 delay time receive data t rxs 100 100 100 setup time (synchronous) receive data t rxh 100 100 100 hold time (synchronous clock input) receive data t rxh 0 0 0 hold time (synchronous clock output) ports output data t pwd 100 100 100 ns figure 17-11 and delay time tpc input data t prs 50 50 50 setup time (synchronous) input data t prh 50 50 50 hold time (synchronous) 435 figure 17-3 output load circuit 436 cr h 5 v r l h8/3032 series output pin c = 90 pf: ports 5, 6, 8, a 19 to a 0 , d 7 to d 0 , ? , , c = 30 pf: ports 9, a, b input/output timing measurement levels ?low: 0.8 v ?high: 2.0 v r = 2.4 k r = 12 k l h w w as rd wr 17.2.3 a/d conversion characteristics table 17-7 lists the a/d conversion characteristics. table 17-7 a/d converter characteristics condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 8 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition b: v cc = 3.0 v to 5.5 v, av cc = 3.0 v to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 10 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition c: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 16 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 16.8 13.4 8.4 s analog input 20 20 20 pf capacitance permissible signal- 10 * 1 10 * 1 10 * 4 k source impedance 5 * 2 5 * 3 5 * 5 nonlinearity error 6.0 6.0 3.0 lsb offset error 4.0 4.0 2.0 lsb full-scale error 4.0 4.0 2.0 lsb quantization error 0.5 0.5 0.5 lsb absolute accuracy 8.0 8.0 4.0 lsb notes: 1. the value is for 4.0 av cc 5.5. 2. the value is for 2.7 av cc < 4.0. 3. the value is for 3.0 av cc < 4.0. 4. the value is for ? 12 mhz. 5. the value is for ? > 12 mhz. 437 17.3 operational timing this section shows timing diagrams. 17.3.1 bus timing bus timing is shown as follows: basic bus cycle: two-state access figure 17-4 shows the timing of the external two-state access cycle. basic bus cycle: three-state access figure 17-5 shows the timing of the external three-state access cycle. basic bus cycle: three-state access with one wait state figure 17-6 shows the timing of the external three-state access cycle with one wait state inserted. 438 figure 17-4 basic bus cycle: two-state access t 1 t 2 t cyc t ch t cl t ad t cf t cr t as1 t as1 t asd t acc3 t asd t acc3 t acc1 t asd t as1 t wdd t wds1 t wsw1 t sd t ah t pch t sd t ah t pch t rdh t rds t pch t sd t ah t wdh a 19 to a 0 as rd (read) d 7 to d 0 (read) wr (write) d 7 to d 0 (write) 439 figure 17-5 basic bus cycle: three-state access t 1 t 2 t 3 t acc4 t acc4 t acc2 t wsw2 t wsd t as2 t wds2 ? a 19 to a 0 as rd (read) d 7 to d 0 (read) wr (write) d 7 to d 0 (write) t rds 440 figure 17-6 basic bus cycle: three-state access with one wait state t 1 t 2 t w t 3 t wts t wts t wth ? a 19 to a 0 as rd (read) d 7 to d 0 (read) wr (write) d 7 to d 0 (write) wait t wth 441 17.3.2 control signal timing control signal timing is shown as follows: reset input timing figure 17-7 shows the reset input timing. reset output timing figure 17-8 shows the reset output timing. interrupt input timing figure 17-9 shows the input timing for nmi and irq 4 to irq 0 . figure 17-7 reset input timing figure 17-8 reset output timing res t ress t ress t resw reso t resd t resow t resd 442 figure 17-9 interrupt input timing ? nmi irq irq e l t nmis t nmih t nmis t nmih t nmis t nmiw nmi irq j irq : edge-sensitive irq : level-sensitive irq (i = 0 to 4) e l i i irq (j = 0 to 2) 443 17.3.3 clock timing clock timing is shown as follows: oscillator settling timing figure 17-10 shows the oscillator settling timing. figure 17-10 oscillator settling timing 17.3.4 tpc and i/o port timing tpc and i/o port timing is shown as follows. figure 17-11 tpc and i/o port input/output timing v cc stby res t osc1 t osc1 t 1 t 2 t 3 ports 1 to 3, 5, a, and b (read) ports 1 to 3, 5, 6, 8, 9, a, and b (write) t prs t prh t pwd 444 17.3.5 itu timing itu timing is shown as follows: itu input/output timing figure 17-12 shows the itu input/output timing. itu external clock input timing figure 17-13 shows the itu external clock input timing. figure 17-12 itu input/output timing figure 17-13 itu clock input timing ? output compare * 1 input capture * 2 t tocd t tics notes: 1. tioca 0 to tioca 4 , tiocb 0 to tiocb 4 , tocxa 4 , tocxb 4 2. tioca 0 to tioca 4 , tiocb 0 to tiocb 4 t tcks t tcks t tckwh t tckwl tclka to tclkd 445 17.3.6 sci input/output timing sci timing is shown as follows: sci input clock timing figure 17-14 shows the sci input clock timing. sci input/output timing (synchronous mode) figure 17-15 shows the sci input/output timing in synchronous mode. figure 17-14 sck input clock timing figure 17-15 sci input/output timing in synchronous mode sck t sckw t scyc t sckr t sckr t scyc t txd t rxs t rxh sck txd (transmit data) rxd (receive data) 446 appendix a instruction set a.1 instruction list operand notation symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement ? transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides e subtraction of the operand on the right from the operand on the left multiplication of the operands on both sides ? division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides ? exclusive logical or of the operands on both sides a not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). 447 condition code notation symbol description changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 not affected by execution of the instruction d varies depending on conditions, described in notes 448 table a-1 instruction set 1. data transfer instructions condition code mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 ? rd8 2 0 2 mov.b rs, rd b rs8 ? rd8 2 0 2 mov.b @ers, rd b @ers ? rd8 2 0 4 mov.b @(d:16, ers), b @(d:16, ers) ? rd8 4 0 6 rd mov.b @(d:24, ers), b @(d:24, ers) ? rd8 8 0 10 rd mov.b @ers+, rd b @ers ? rd8 2 0 6 ers32+1 ? ers32 mov.b @aa:8, rd b @aa:8 ? rd8 2 0 4 mov.b @aa:16, rd b @aa:16 ? rd8 4 0 6 mov.b @aa:24, rd b @aa:24 ? rd8 6 0 8 mov.b rs, @erd b rs8 ? @erd 2 0 4 mov.b rs, @(d:16, b rd8 ? @(d:16, erd) 4 0 6 erd) mov.b rs, @(d:24, b rd8 ? @(d:24, erd) 8 0 10 erd) mov.b rs, @erd b erd32? ? erd32 2 0 6 rs8 ? @erd mov.b rs, @aa:8 b rs8 ? @aa:8 2 0 4 mov.b rs, @aa:16 b rs8 ? @aa:16 4 0 6 mov.b rs, @aa:24 b rs8 ? @aa:24 6 0 8 mov.w #xx:16, rd w #xx:16 ? rd16 4 0 4 mov.w rs, rd w rs16 ? rd16 2 0 2 mov.w @ers, rd w @ers ? rd16 2 0 4 mov.w @(d:16, ers), w @(d:16, ers) ? rd16 4 0 6 rd mov.w @(d:24, ers), w @(d:24, ers) ? rd16 8 0 10 rd mov.w @ers+, rd w @ers ? rd16 2 0 6 ers32+2 ? @erd32 mov.w @aa:16, rd w @aa:16 ? rd16 4 0 6 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 449 table a-1 instruction set (cont) condition code mnemonic operation i h n z v c mov.w @aa:24, rd w @aa:24 ? rd16 6 0 8 mov.w rs, @erd w rs16 ? @erd 2 0 4 mov.w rs, @(d:16, w rs16 ? @(d:16, erd) 4 0 6 erd) mov.w rs, @(d:24, w rs16 ? @(d:24, erd) 8 0 10 erd) mov.w rs, @?rd w erd32? ? erd32 2 0 6 rs16 ? @erd mov.w rs, @aa:16 w rs16 ? @aa:16 4 0 6 mov.w rs, @aa:24 w rs16 ? @aa:24 6 0 8 mov.l #xx:32, rd l #xx:32 ? rd32 6 0 6 mov.l ers, erd l ers32 ? erd32 2 0 2 mov.l @ers, erd l @ers ? erd32 4 0 8 mov.l @(d:16, ers), l @(d:16, ers) ? erd32 6 0 10 erd mov.l @(d:24, ers), l @(d:24, ers) ? erd32 10 0 14 erd mov.l @ers+, erd l @ers ? erd32 4 0 10 ers32+4 ? ers32 mov.l @aa:16, erd l @aa:16 ? erd32 6 0 10 mov.l @aa:24, erd l @aa:24 ? erd32 8 0 12 mov.l ers, @erd l ers32 ? @erd 4 0 8 mov.l ers, @(d:16, l ers32 ? @(d:16, erd) 6 0 10 erd) mov.l ers, @(d:24, l ers32 ? @(d:24, erd) 10 0 14 erd) mov.l ers, @?rd l erd32? ? erd32 4 0 10 ers32 ? @erd mov.l ers, @aa:16 l ers32 ? @aa:16 6 0 10 mov.l ers, @aa:24 l ers32 ? @aa:24 8 0 12 pop.w rn w @sp ? rn16 2 0 6 sp+2 ? sp pop.l ern l @sp ? ern32 4 0 10 sp+4 ? sp #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 450 table a-1 instruction set (cont) condition code mnemonic operation i h n z v c push.w rn w sp? ? sp 2 0 6 rn16 ? @sp push.l ern l sp? ? sp 4 0 10 ern32 ? @sp movfpe @aa:16, b cannot be used in the 4 cannot be used in the h8/3032 rd h8/3032 series series movtpe rs, b cannot be used in the 4 cannot be used in the h8/3032 @aa:16 h8/3032 series series 2. arithmetic instructions condition code mnemonic operation i h n z v c add.b #xx:8, rd b rd8+#xx:8 ? rd8 2 2 add.b rs, rd b rd8+rs8 ? rd8 2 2 add.w #xx:16, rd w rd16+#xx:16 ? rd16 4 1 ???? 4 add.w rs, rd w rd16+rs16 ? rd16 2 1 ???? 2 add.l #xx:32, erd l erd32+#xx:32 ? 6 2 ???? 6 erd32 add.l ers, erd l erd32+ers32 ? 2 2 ???? 2 erd32 addx.b #xx:8, rd b rd8+#xx:8 +c ? rd8 2 3 ?? 2 addx.b rs, rd b rd8+rs8 +c ? rd8 2 3 ?? 2 adds.l #1, erd l erd32+1 ? erd32 2 2 adds.l #2, erd l erd32+2 ? erd32 2 2 adds.l #4, erd l erd32+4 ? erd32 2 2 inc.b rd b rd8+1 ? rd8 2 ? inc.w #1, rd w rd16+1 ? rd16 2 ? inc.w #2, rd w rd16+2 ? rd16 2 ? #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 451 t i able a-1 instruction set (cont) condition code mnemonic operation i h n z v c inc.l #1, erd l erd32+1 ? erd32 2 ? inc.l #2, erd l erd32+2 ? erd32 2 ? daa rd b rd8 decimal adjust 2 * * ? ? rd8 sub.b rs, rd b rd8?s8 ? rd8 2 2 sub.w #xx:16, rd w rd16?xx:16 ? rd16 4 1 ???? 4 sub.w rs, rd w rd16?s16 ? rd16 2 1 ???? 2 sub.l #xx:32, erd l erd32?xx:32 6 2 ???? 6 ? erd32 sub.l ers, erd l erd32?rs32 2 2 ???? 2 ? erd32 subx.b #xx:8, rd b rd8?xx:8? ? rd8 2 3 ?? 2 subx.b rs, rd b rd8?s8? ? rd8 2 3 ?? 2 subs.l #1, erd l erd32? ? erd32 2 2 subs.l #2, erd l erd32? ? erd32 2 2 subs.l #4, erd l erd32? ? erd32 2 2 dec.b rd b rd8? ? rd8 2 ? dec.w #1, rd w rd16? ? rd16 2 ? dec.w #2, rd w rd16? ? rd16 2 ? dec.l #1, erd l erd32? ? erd32 2 ? dec.l #2, erd l erd32? ? erd32 2 ? das.rd b rd8 decimal adjust 2 * * ? ? rd8 mulxu. b rs, rd b rd8 rs8 ? rd16 2 14 (unsigned multiplication) mulxu. w rs, erd w rd16 rs16 ? erd32 2 22 (unsigned multiplication) mulxs. b rs, rd b rd8 rs8 ? rd16 4 16 (signed multiplication) mulxs. w rs, erd w rd16 rs16 ? erd32 4 24 (signed multiplication) divxu. b rs, rd b rd16 ? rs8 ? rd16 2 67 14 (rdh: remainder, rdl: quotient) (unsigned division ) #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 452 table a-1 instruction set (cont) condition code mnemonic operation i h n z v c divxu. w rs, erd w erd32 ? rs16 ? erd32 2 67 22 (ed: remainder, rd: quotient) (unsigned division) divxs. b rs, rd b rd16 ? rs8 ? rd16 4 87 16 (rdh: remainder, rdl: quotient) (signed division) divxs. w rs, erd w erd32 ? rs16 ? erd32 4 87 24 (ed: remainder, rd: quotient) (signed division) cmp.b #xx:8, rd b rd8?xx:8 2 2 cmp.b rs, rd b rd8?s8 2 2 cmp.w #xx:16, rd w rd16?xx:16 4 1 ???? 4 cmp.w rs, rd w rd16?s16 2 1 ???? 2 cmp.l #xx:32, erd l erd32?xx:32 6 2 ???? 4 cmp.l ers, erd l erd32?rs32 2 2 ???? 2 neg.b rd b 0?d8 ? rd8 2 2 neg.w rd w 0?d16 ? rd16 2 2 neg.l erd l 0?rd32 ? erd32 2 2 extu.w rd w 0 ? ( table a-1 instruction set (cont) 3. logic instructions condition code mnemonic operation i h n z v c and.b #xx:8, rd b rd8 #xx:8 ? rd8 2 0 2 and.b rs, rd b rd8 rs8 ? rd8 2 0 2 and.w #xx:16, rd w rd16 #xx:16 ? rd16 4 0 4 and.w rs, rd w rd16 rs16 ? rd16 2 0 2 and.l #xx:32, erd l erd32 #xx:32 ? erd32 6 0 6 and.l ers, erd l erd32 ers32 ? erd32 4 0 4 or.b #xx:8, rd b rd8 #xx:8 ? rd8 2 0 2 or.b rs, rd b rd8 rs8 ? rd8 2 0 2 or.w #xx:16, rd w rd16 #xx:16 ? rd16 4 0 4 or.w rs, rd w rd16 rs16 ? rd16 2 0 2 or.l #xx:32, erd l erd32 #xx:32 ? erd32 6 0 6 or.l ers, erd l erd32 ers32 ? erd32 4 0 4 xor.b #xx:8, rd b rd8 ? #xx:8 ? rd8 2 0 2 xor.b rs, rd b rd8 ? rs8 ? rd8 2 0 2 xor.w #xx:16, rd w rd16 ? #xx:16 ? rd16 4 0 4 xor.w rs, rd w rd16 ? rs16 ? rd16 2 0 2 xor.l #xx:32, erd l erd32 ? #xx:32 ? erd32 6 0 6 xor.l ers, erd l erd32 ? ers32 ? erd32 4 0 4 not.b rd b rd8 ? rd8 2 0 2 not.w rd w rd16 ? rd16 2 0 2 not.l erd l rd32 ? rd32 2 0 2 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 454 table a-1 instruction set (cont) 4. shift instructions condition code mnemonic operation i h n z v c shal.b rd b 2 2 shal.w rd w 2 2 shal.l erd l 2 2 shar.b rd b 2 0 2 shar.w rd w 2 0 2 shar.l erd l 2 0 2 shll.b rd b 2 0 2 shll.w rd w 2 0 2 shll.l erd l 2 0 2 shlr.b rd b 2 0 2 shlr.w rd w 2 0 2 shlr.l erd l 2 0 2 rotxl.b rd b 2 0 2 rotxl.w rd w 2 0 2 rotxl.l erd l 2 0 2 rotxr.b rd b 2 0 2 rotxr.w rd w 2 0 2 rotxr.l erd l 2 0 2 rotl.b rd b 2 0 2 rotl.w rd w 2 0 2 rotl.l erd l 2 0 2 rotr.b rd b 2 0 2 rotr.w rd w 2 0 2 rotr.l erd l 2 0 2 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size msb lsb 0 c c msb lsb msb lsb 0 c 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb 455 table a-1 instruction set (cont) 5. bit manipulation instructions condition code mnemonic operation i h n z v c bset #xx:3, rd b (#xx:3 of rd8) ? 1 2 2 bset #xx:3, @erd b (#xx:3 of @erd) ? 1 4 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 1 4 8 bset rn, rd b (rn8 of rd8) ? 1 2 2 bset rn, @erd b (rn8 of @erd) ? 1 4 8 bset rn, @aa:8 b (rn8 of @aa:8) ? 1 4 8 bclr #xx:3, rd b (#xx:3 of rd8) ? 0 2 2 bclr #xx:3, @erd b (#xx:3 of @erd) ? 0 4 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 0 4 8 bclr rn, rd b (rn8 of rd8) ? 0 2 2 bclr rn, @erd b (rn8 of @erd) ? 0 4 8 bclr rn, @aa:8 b (rn8 of @aa:8) ? 0 4 8 bnot #xx:3, rd b (#xx:3 of rd8) ? 2 2 (#xx:3 of rd8) bnot #xx:3, @erd b (#xx:3 of @erd) ? 4 8 (#xx:3 of @erd) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 4 8 (#xx:3 of @aa:8) bnot rn, rd b (rn8 of rd8) ? 2 2 (rn8 of rd8) bnot rn, @erd b (rn8 of @erd) ? 4 8 (rn8 of @erd) bnot rn, @aa:8 b (rn8 of @aa:8) ? 4 8 (rn8 of @aa:8) btst #xx:3, rd b (#xx:3 of rd8) ? z 2 2 btst #xx:3, @erd b (#xx:3 of @erd) ? z 4 6 btst #xx:3, @aa:8 b (#xx:3 of @aa:8) ? z 4 6 btst rn, rd b (rn8 of @rd8) ? z 2 2 btst rn, @erd b (rn8 of @erd) ? z 4 6 btst rn, @aa:8 b (rn8 of @aa:8) ? z 4 6 bld #xx:3, rd b (#xx:3 of rd8) ? c 2 2 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 456 table a-1 instruction set (cont) condition code mnemonic operation i h n z v c bld #xx:3, @erd b (#xx:3 of @erd) ? c 4 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 6 bild #xx:3, rd b (#xx:3 of rd8) ? c 2 2 bild #xx:3, @erd b (#xx:3 of @erd) ? c 4 6 bild #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 6 bst #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bst #xx:3, @red b c ? (#xx:3 of @erd) 4 8 bst #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bist #xx:3, @erd b c ? (#xx:3 of @erd24) 4 8 bist #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 band #xx:3, @erd b c (#xx:3 of @erd24) ? c 4 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 biand #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 biand #xx:3, @erd b c (#xx:3 of @erd24) ? c 4 6 biand #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bor #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 bor #xx:3, @erd b c (#xx:3 of @erd24) ? c 4 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bior #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 bior #xx:3, @erd b c (#xx:3 of @erd24) ? c 4 6 bior #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bxor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 2 bxor #xx:3, @erd b c ? (#xx:3 of @erd24) ? c 4 6 bxor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 6 bixor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 2 bixor #xx:3, @erd b c ? (#xx:3 of @erd24) ? c 4 6 bixor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 6 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 457 table a-1 instruction set (cont) 6. branching instructions condition code mnemonic operation i h n z v c bra d:8 (bt d:8) always 2 4 bra d:16 (bt d:16) 4 6 brn d:8 (bf d:8) never 2 4 brn d:16 (bf d:16) 4 6 bhi d:8 c z = 0 2 4 bhi d:16 4 6 bls d:8 c z = 1 2 4 bls d:16 4 6 bcc d:8 (bhs d:8) c = 0 2 4 bcc d:16 (bhs d:16) 4 6 bcs d:8 (blo d:8) c = 1 2 4 bcs d:16 (blo d:16) 4 6 bne d:8 z = 0 2 4 bne d:16 4 6 beq d:8 z = 1 2 4 beq d:16 4 6 bvc d:8 v = 0 2 4 bvc d:16 4 6 bvs d:8 v = 1 2 4 bvs d:16 4 6 bpl d:8 n = 0 2 4 bpl d:16 4 6 bmi d:8 n = 1 2 4 bmi d:16 4 6 bge d:8 n ? v = 0 2 4 bge d:16 4 6 blt d:8 n ? v = 1 2 4 blt d:16 4 6 bgt d:8 2 4 bgt d:16 4 6 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size z (n ? v) = 0 if condition is true then pc ? pc+d else next; 458 table a-1 instruction set (cont) condition code mnemonic operation i h n z v c ble d:8 2 4 ble d:16 4 6 jmp @ern pc ? ern 2 4 jmp @aa:24 pc ? aa:24 4 6 jmp @@aa:8 pc ? @aa:8 2 8 10 bsr d:8 pc ? @?p 2 6 8 pc ? pc+d:8 bsr d:16 pc ? @?p 4 8 10 pc ? pc+d:16 jsr @ern pc ? @?p 2 6 8 pc ? @ern jsr @aa:24 pc ? @?p 4 8 10 pc ? @aa:24 jsr @@aa:8 pc ? @?p 2 8 12 pc ? @aa:8 rts pc ? @sp+ 2 8 10 #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size z (n ? v) = 1 if condition is true then pc ? pc+d else next; 459 table a-1 instruction set (cont) 7. system control instructions condition code mnemonic operation i h n z v c trapa #x:2 pc ? @?p 2 14 16 ccr ? @?p table a-1 instruction set (cont) 8. block transfer instructions condition code mnemonic operation i h n z v c eepmov. b if r4l 0 then 4 8+ repeat @r5 ? @r6 4n * 2 r5+1 ? r5 r6+1 ? r6 r4l? ? r4l until r4l=0 else next eepmov. w if r4 0 then 4 8+ repeat @r5 ? @r6 4n * 2 r5+1 ? r5 r6+1 ? r6 r4l? ? r4 until r4=0 else next notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. for other cases see section a.3, number of states required for execution. 2. n is the value set in register r4l or r4. 1 set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. 2 set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. 3 retains its previous value when the result is zero; otherwise cleared to 0. 4 set to 1 when the adjustment produces a carry; otherwise retains its previous value. 5 the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. 6 set to 1 when the divisor is negative; otherwise cleared to 0. 7 set to 1 when the divisor is zero; otherwise cleared to 0. 8 set to 1 when the quotient is negative; otherwise cleared to 0. #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa implied addressing mode and instruction length (bytes) normal no. of states * 1 advanced operand size 461 a.2 operation code maps table a-2 operation code map (1) 462 ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu.b bset brn divxu.b bnot stc bhi mulxu.w bclr ldc bls divxu.w btst org or.b bcc rts or.w xorc xor.b bcs bsr xor.w bor bior bxor bixor band biand andc and.b bne rte and.w ldc beq trapa bld bild bst bist bvc mov.b mov.b/w bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp 463 table a-2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) add mov sub cmp.l bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg 464 table a-2 operation code map (3) ah albh blch c 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc lbc ldc ldc stc stc stc a.3 number of states required for execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8/300h cpu. table a-3 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a-2 indicates the number of states required per cycle according to the bus size. the number of states required for execution of an instruction can be calculated from these two tables as follows: number of states = i s i + j s j + k s k + l s l + m s m + n s n examples of calculation of number of states required for execution examples: advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. bset #0, @fffffc7:8 from table a-3, i = l = 2 and j = k = m = n = 0 from table a-2, s i = 4 and s l = 3 number of states = 2 4 + 2 3 = 14 jsr @@30 from table a-3, i = j = k = 2 and l = m = n = 0 from table a-2, s i = s j = s k = 4 number of states = 2 4 + 2 4 + 2 4 = 24 465 table a-2 number of states per cycle access conditions external device 8-bit bus 16-bit bus on-chip 8-bit 16-bit 2-state 3-state 2-state 3-state cycle memory bus bus access access access access instruction fetch s i 2 6346 + 2m23 + m branch address read s j stack operation s k byte data access s l 3 2 3 + m word data access s m 6 4 6 + 2m internal operation s n 1 legend m: number of wait states inserted into external device access on-chip sup- porting module 466 table a-3 number of cycles per instruction instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w #xx:16, rd 2 add.w rs, rd 1 add.l #xx:32, erd 3 add.l ers, erd 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd 1 addx rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 and.w #xx:16, rd 2 and.w rs, rd 1 and.l #xx:32, erd 3 and.l ers, erd 2 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @erd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 467 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bcc bra d:16 (bt d:16) 2 2 brn d:16 (bf d:16) 2 2 bhi d:16 2 2 bls d:16 2 2 bcc d:16 (bhs d:16) 2 2 bcs d:16 (blo d:16) 2 2 bne d:16 2 2 beq d:16 2 2 bvc d:16 2 2 bvs d:16 2 2 bpl d:16 2 2 bmi d:16 2 2 bge d:16 2 2 blt d:16 2 2 bgt d:16 2 2 ble d:16 2 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @erd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @erd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @erd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @erd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:8, rd 1 bior #xx:8, @erd 2 1 bior #xx:8, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @erd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @erd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @erd 2 1 bld #xx:3, @aa:8 2 1 468 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bnot bnot #xx:3, rd 1 bnot #xx:3, @erd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @erd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @erd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @erd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @erd 2 2 bset rn, @aa:8 2 2 bsr bsr d:8 normal 2 1 advanced 2 2 bsr d:16 normal 2 1 2 advanced 2 2 2 bst bst #xx:3, rd 1 bst #xx:3, @erd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @erd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @erd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @erd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp.b #xx:8, rd 1 cmp.b rs, rd 1 cmp.w #xx:16, rd 2 cmp.w rs, rd 1 cmp.l #xx:32, erd 3 cmp.l ers, erd 1 daa daa rd 1 das das rd 1 469 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n dec dec.b rd 1 dec.w #1/2, rd 1 dec.l #1/2, erd 1 divxs divxs.b rs, rd 2 12 divxs.w rs, erd 2 20 divxu divxu.b rs, rd 1 12 divxu.w rs, erd 1 20 eepmov eepmov.b 2 2n + 2 * 1 eepmov.w 2 2n + 2 * 1 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2, rd 1 inc.l #1/2, erd 1 jmp jmp @ern 2 jmp @aa:24 2 2 jmp @@aa:8 normal 2 1 2 advanced 2 2 2 jsr jsr @ern normal 2 1 advanced 2 2 jsr @aa:24 normal 2 1 2 advanced 2 2 2 jsr @@aa:8 normal 2 1 1 advanced 2 2 2 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 ldc @ers, ccr 2 1 ldc @(d:16, ers), ccr 3 1 ldc @(d:24, ers), ccr 5 1 ldc @ers+, ccr 2 1 2 ldc @aa:16, ccr 3 1 ldc @aa:24, ccr 4 1 470 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @ers, rd 1 1 mov.b @(d:16, ers), rd 21 mov.b @(d:24, ers), rd 41 mov.b @ers+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b @aa:24, rd 3 1 mov.b rs, @erd 1 1 mov.b rs, @(d:16, erd) 21 mov.b rs, @(d:24, erd) 41 mov.b rs, @?rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.b rs, @aa:24 3 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @ers, rd 1 1 mov.w @(d:16, ers), rd 21 mov.w @(d:24, ers), rd 41 mov.w @ers+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w @aa:24, rd 3 1 mov.w rs, @erd 1 1 mov.w rs, @(d:16, erd) 21 mov.w rs, @(d:24, erd) 41 mov.w rs, @?rd 1 1 2 mov.w rs, @aa:16 2 1 mov.w rs, @aa:24 3 1 mov.l #xx:32, erd 3 mov.l ers, erd 1 mov.l @ers, erd 2 2 mov.l @(d:16, ers), erd 32 mov.l @(d:24, ers), erd 52 mov.l @ers+, erd 2 2 2 mov.l @aa:16, erd 3 2 mov.l @aa:24, erd 4 2 mov.l ers, @erd 2 2 mov.l ers, @(d:16, erd) 32 mov.l ers, @(d:24, erd) 52 mov.l ers, @?rd 2 2 2 mov.l ers, @aa:16 3 2 mov.l ers, @aa:24 4 2 471 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n movfpe movfpe @aa:16, rd * 2 21 movtpe movtpe rs, @aa:16 * 2 21 mulxs mulxs.b rs, rd 2 12 mulxs.w rs, erd 2 20 mulxu mulxu.b rs, rd 1 12 mulxu.w rs, erd 1 20 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 or.w #xx:16, rd 2 or.w rs, rd 1 or.l #xx:32, erd 3 or.l ers, erd 2 orc orc #xx:8, ccr 1 pop pop.w rn 1 1 2 pop.l ern 2 2 2 push push.w rn 1 1 2 push.l ern 2 2 2 rotl rotl.b rd 1 rotl.w rd 1 rotl.l erd 1 rotr rotr.b rd 1 rotr.w rd 1 rotr.l erd 1 rotxl rotxl.b rd 1 rotxl.w rd 1 rotxl.l erd 1 rotxr rotxr.b rd 1 rotxr.w rd 1 rotxr.l erd 1 rte rte 2 2 2 472 table a-3 number of cycles per instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n rts rts normal 2 1 2 advanced 2 2 2 shal shal.b rd 1 shal.w rd 1 shal.l erd 1 shar shar.b rd 1 shar.w rd 1 shar.l erd 1 shll shll.b rd 1 shll.w rd 1 shll.l erd 1 shlr shlr.b rd 1 shlr.w rd 1 shlr.l erd 1 sleep sleep 1 stc stc ccr, rd 1 stc ccr, @erd 2 1 stc ccr, @(d:16, erd) 3 1 stc ccr, @(d:24, erd) 5 1 stc ccr, @?rd 2 1 2 stc ccr, @aa:16 3 1 stc ccr, @aa:24 4 1 sub sub.b rs, rd 1 sub.w #xx:16, rd 2 sub.w rs, rd 1 sub.l #xx:32, erd 3 sub.l ers, erd 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd 1 subx rs, rd 1 trapa trapa #x:2 normal 2 1 2 4 advanced 2 2 2 4 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xor.w #xx:16, rd 2 xor.w rs, rd 1 xor.l #xx:32, erd 3 xor.l ers, erd 2 xorc xorc #xx:8, ccr 1 notes: 1. n is the value set in register r4l or r4. the source and destination are accessed n + 1 times each. 2. not available in the h8/3032 series. 473 appendix b register field b.1 register addresses and bit names data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'1c h'1d h'1e h'1f h'20 h'21 h'22 h'23 h'24 h'25 h'26 h'27 h'28 h'29 h'2a h'2b h'2c h'2d h'2e h'2f h'30 h'31 h'32 h'33 h'34 h'35 h'36 h'37 h'38 h'39 h'3a legend dmac: dma controller (continued on next page) 474 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'3b h'3c h'3d h'3e h'3f h'40 h'41 h'42 h'43 h'44 h'45 h'46 h'47 h'48 h'49 h'4a h'4b h'4c h'4d h'4e h'4f h'50 h'51 h'52 h'53 h'54 h'55 h'56 h'57 h'58 h'59 h'5a h'5b h'5c h'5d h'5e h'5f (continued on next page) 475 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'60 tstr 8 str4 str3 str2 str1 str0 h'61 tsnc 8 sync4 sync3 sync2 sync1 sync0 h'62 tmdr 8 mdf fdir pwm4 pwm3 pwm2 pwm1 pwm0 h'63 tfcr 8 cmd1 cmd0 bfb4 bfa4 bfb3 bfa3 h'64 tcr0 8 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'65 tior0 8 iob2 iob1 iob0 ioa2 ioa1 ioa0 h'66 tier0 8 ovie imieb imiea h'67 tsr0 8 ?vf imfb imfa h'68 tcnt0h 16 h'69 tcnt0l h'6a gra0h 16 h'6b gra0l h'6c grb0h 16 h'6d grb0l h'6e tcr1 8 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'6f tior1 8 iob2 iob1 iob0 ioa2 ioa1 ioa0 h'70 tier1 8 ovie imieb imiea h'71 tsr1 8 ?vf imfb imfa h'72 tcnt1h 16 h'73 tcnt1l h'74 gra1h 16 h'75 gra1l h'76 grb1h 16 h'77 grb1l h'78 tcr2 8 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'79 tior2 8 iob2 iob1 iob0 ioa2 ioa1 ioa0 h'7a tier2 8 ovie imieb imiea h'7b tsr2 8 ?vf imfb imfa h'7c tcnt2h 16 h'7d tcnt2l h'7e gra2h 16 h'7f gra2l h'80 grb2h 16 h'81 grb2l legend itu: 16-bit integrated timer unit (continued on next page) itu (all channels) itu channel 0 itu channel 1 itu channel 2 476 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'82 tcr3 8 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'83 tior3 8 iob2 iob1 iob0 ioa2 ioa1 ioa0 h'84 tier3 8 ovie imieb imiea h'85 tsr3 8 ?vf imfb imfa h'86 tcnt3h 16 h'87 tcnt3l h'88 gra3h 16 h'89 gra3l h'8a grb3h 16 h'8b grb3l h'8c bra3h 16 h'8d bra3l h'8e brb3h 16 h'8f brb3l h'90 toer 8 exb4 exa4 eb3 eb4 ea4 ea3 h'91 tocr 8 xtgd ols4 ols3 h'92 tcr4 8 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'93 tior4 8 iob2 iob1 iob0 ioa2 ioa1 ioa0 h'94 tier4 8 ovie imieb imiea h'95 tsr4 8 ovf imfb imfa h'96 tcnt4h 16 h'97 tcnt4l h'98 gra4h 16 h'99 gra4l h'9a grb4h 16 h'9b grb4l h'9c bra4h 16 h'9d bra4l h'9e brb4h 16 h'9f brb4l legend itu: 16-bit integrated timer unit (continued on next page) itu channel 3 itu (all channels) itu channel 4 477 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'a0 tpmr 8 g3nov g2nov g1nov g0nov tpc h'a1 tpcr 8 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 h'a2 nderb 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'a3 ndera 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'a4 ndrb * 1 8 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 8 ndr15 ndr14 ndr13 ndr12 h'a5 ndra * 1 8 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 8 ndr7 ndr6 ndr5 ndr4 h'a6 ndrb * 1 8 8 ndr11 ndr10 ndr9 ndr8 h'a7 ndra * 1 8 8 ndr3 ndr2 ndr1 ndr0 h'a8 tcsr * 2 8 ovf wt/ it tme cks2 cks1 cks0 wdt h'a9 tcnt * 2 8 h'aa h'ab rstcsr * 3 8 wrst rstoe h'ac h'ad h'ae h'af h'b0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 0 h'b1 brr 8 h'b2 scr 8 tie rie te re mpie teie cke1 cke0 h'b3 tdr 8 h'b4 ssr 8 tdre rdrf orer fer per tend mpb mpbt h'b5 rdr 8 h'b6 h'b7 notes: 1. the address depends on the output trigger setting. 2. for write access to tcsr and tcnt, see section 10.2.4, notes on register access. 3. for write access to rstcsr, see section 10.2.4, notes on register access. legend tpc: programmable timing pattern controller wdt: watchdog timer sci: serial communication interface (continued on next page) 478 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'b8 h'b9 h'ba h'bb h'bc h'bd h'be h'bf h'c0 p1ddr 8 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'c1 p2ddr 8 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'c2 p1dr 8 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'c3 p2dr 8 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'c4 p3ddr 8 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 2 h'c5 h'c6 p3dr 8 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h'c7 h'c8 p5ddr 8 p5 7 ddr p5 6 ddr p5 5 ddr p5 4 ddr p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'c9 p6ddr 8 p6 5 ddr p6 4 ddr p6 3 ddr p6 0 ddr port 6 h'ca p5dr 8 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 port 5 h'cb p6dr 8 p6 5 p6 4 p6 3 p6 0 port 6 h'cc h'cd p8ddr 8 ?8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'ce p7dr 8 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'cf p8dr 8 p8 3 p8 2 p8 1 p8 0 port 8 h'd0 p9ddr 8 ?9 4 ddr p9 2 ddr p9 0 ddr port 9 h'd1 paddr 8 pa 7 ddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr port a h'd2 p9dr 8 ?9 4 ?9 2 ?9 0 port 9 h'd3 padr 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 port a h'd4 pbddr 8 pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr port b h'd5 pcddr 8 pc 7 ddr pc 6 ddr pc 5 ddr pc 4 ddr pc 3 ddr pc 2 ddr pc 1 ddr pc 0 ddr port c h'd6 pbdr 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b h'd7 pcdr 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 port c (continued on next page) 479 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'd8 p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'd9 h'da h'db p5pcr 8 p5 3 pcr p5 2 pcr p5 1 pcr p5 0 pcr port 5 h'dc h'dd h'de h'df h'e0 addrah 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'e1 addral 8 ad1 ad0 h'e2 addrbh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e3 addrbl 8 ad1 ad0 h'e4 addrch 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e5 addrcl 8 ad1 ad0 h'e6 addrdh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'e7 addrdl 8 ad1 ad0 h'e8 adcsr 8 adf adie adst scan cks ch2 ch1 ch0 h'e9 adcr 8 trge h'ea h'eb h'ec abwcr 8 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller h'ed astcr 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'ee wcr 8 wms1 wms0 wc1 wc0 h'ef wcer 8 wce7 wce6 wce5 wce4 wce3 wce2 wce1 wce0 legend a/d: a/d converter (continued on next page) 480 (continued from preceding page) data bit names address register bus (low) name width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'f0 h'f1 mdcr 8 mds1 mds0 system control h'f2 syscr 8 ssby sts2 sts1 sts0 ue nmieg rame h'f3 h'f4 iscr 8 irq4sc irq3sc irq2sc irq1sc irq0sc i h'f5 ier 8 irq4e irq3e irq2e irq1e irq0e h'f6 isr 8 irq4f irq3f irq2f irq1f irq0f h'f7 h'f8 ipra 8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 h'f9 iprb 8 iprb7 iprb6 iprb3 iprb1 h'fa h'fb h'fc h'fd h'fe h'ff interrupt controller interrupt controller 481 b.2 register descriptions tstr timer start register h'60 itu (all channels) register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 1 6 1 5 1 4 str4 0 r/w 3 str3 0 r/w 0 str0 0 r/w 2 str2 0 r/w 1 str1 0 r/w counter start 0 0 tcnt0 is halted 1 tcnt0 is counting counter start 3 0 tcnt3 is halted 1 tcnt3 is counting counter start 1 0 tcnt1 is halted 1 tcnt1 is counting counter start 2 0 tcnt2 is halted 1 tcnt2 is counting counter start 4 0 tcnt4 is halted 1 tcnt4 is counting 482 tstr?imer start register h'60 itu (all channels) bit initial value read/write 7 1 6 1 5 1 4 str4 0 r/w 3 str3 0 r/w 0 str0 0 r/w 2 str2 0 r/w 1 str1 0 r/w counter start 0 0 tcnt0 is halted 1 tcnt0 is counting counter start 3 0 tcnt3 is halted 1 tcnt3 is counting counter start 1 0 tcnt1 is halted 1 tcnt1 is counting counter start 2 0 tcnt2 is halted 1 tcnt2 is counting counter start 4 0 tcnt4 is halted 1 tcnt4 is counting 483 tsnc?imer synchro register h'61 itu (all channels) bit initial value read/write 7 1 6 1 5 1 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w timer sync 0 0 tcnt0 operates independently 1 tcnt0 is synchronized timer sync 3 0 tcnt3 operates independently 1 tcnt3 is synchronized timer sync 1 0 tcnt1 operates independently 1 tcnt1 is synchronized timer sync 2 0 tcnt2 operates independently 1 tcnt2 is synchronized timer sync 4 0 tcnt4 operates independently 1 tcnt4 is synchronized 484 tmdr?imer mode register h'62 itu (all channels) bit initial value read/write 7 1 6 mdf 0 r/w 5 fdir 0 r/w 4 pwm4 0 r/w 3 pwm3 0 r/w 0 pwm0 0 r/w 2 pwm2 0 r/w 1 pwm1 0 r/w pwm mode 0 0 channel 0 operates normally 1 channel 0 operates in pwm mode pwm mode 3 0 channel 3 operates normally 1 channel 3 operates in pwm mode pwm mode 1 0 channel 1 operates normally 1 channel 1 operates in pwm mode pwm mode 2 0 channel 2 operates normally 1 channel 2 operates in pwm mode pwm mode 4 0 channel 4 operates normally 1 channel 4 operates in pwm mode flag direction 0 ovf is set to 1 in tsr2 when tcnt2 overflows or underflows 1 ovf is set to 1 in tsr2 when tcnt2 overflows phase counting mode flag 0 channel 2 operates normally 1 channel 2 operates in phase counting mode 485 tfcr?imer function control register h'63 itu (all channels) bit initial value read/write 7 1 6 1 5 cmd1 0 r/w 4 cmd0 0 r/w 3 bfb4 0 r/w 0 bfa3 0 r/w 2 bfa4 0 r/w 1 bfb3 0 r/w buffer mode a3 0 gra3 operates normally 1 gra3 is buffered by bra3 buffer mode b4 0 grb4 operates normally 1 grb4 is buffered by brb4 buffer mode b3 0 grb3 operates normally 1 grb3 is buffered by brb3 buffer mode a4 0 gra4 operates normally 1 gra4 is buffered by bra4 combination mode 1 and 0 channels 3 and 4 operate normally channels 3 and 4 operate together in complementary pwm mode channels 3 and 4 operate together in reset-synchronized pwm mode bit 5 0 1 bit 4 0 1 0 1 operating mode of channels 3 and 4 cmd1 cmd0 486 tcr0?imer control register 0 h'64 itu0 bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w timer prescaler 2 to 0 clock edge 1 and 0 counter clear 1 and 0 tcnt is not cleared tcnt is cleared by grb compare match or input capture synchronous clear: bit 6 0 1 bit 5 0 0 1 tcnt clear source cclr1 cclr0 tcnt is cleared by gra compare match or input capture 1 rising edges counted both edges counted bit 4 0 1 bit 3 0 counted edges of external clock ckeg1 ckeg0 falling edges counted 1 tpsc2 1 tcnt clock source internal clock: internal clock: ?2 internal clock: ?4 internal clock: ?8 external clock a: tclka input external clock b: tclkb input external clock c: tclkc input bit 2 tpsc1 0 1 0 1 bit 1 tpsc0 0 1 0 1 0 1 bit 0 0 external clock d: tclkd input 1 0 tcnt is cleared in synchronization with other synchronized timers 487 tior0?imer i/o control register 0 h'65 itu0 bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w i/o control a2 to a0 ioa2 1 gra function gra is an output compare register gra is an input capture register ioa1 0 1 0 1 bit 1 ioa0 0 1 0 1 0 1 bit 0 0 1 0 bit 2 no output at compare match 0 output at gra compare match 1 output at gra compare match output toggles at gra compare match gra captures rising edge of input gra captures falling edge of input gra captures both edges of input i/o control b2 to b0 iob2 1 grb function grb is an output compare register grb is an input capture register iob1 0 1 0 1 bit 5 iob0 0 1 0 1 0 1 bit 4 0 1 0 bit 6 no output at compare match 0 output at grb compare match 1 output at grb compare match output toggles at grb compare match grb captures rising edge of input grb captures falling edge of input grb captures both edges of input 488 tier0?imer interrupt enable register 0 h'66 itu0 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imiea 0 r/w 2 ovie 0 r/w 1 imieb 0 r/w input capture/compare match interrupt enable a 0 imia interrupt requested by imfa is disabled 1 imia interrupt requested by imfa is enabled input capture/compare match interrupt enable b 0 imib interrupt requested by imfb is disabled 1 imib interrupt requested by imfb is enabled overflow interrupt enable 0 ovi interrupt requested by ovf is disabled 1 ovi interrupt requested by ovf is enabled 489 tsr0?imer status register 0 h'67 itu0 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imfa 0 r/(w) 2 ovf 0 r/(w) 1 imfb 0 r/(w) input capture/compare match flag a 0 [clearing condition] overflow flag *** read imfa when imfa = 1, then write 0 in imfa 1 [setting conditions] tcnt = gra when gra functions as a compare match register. tcnt value is transferred to gra by an input capture signal, when gra functions as an input capture register. input capture/compare match flag b 0 [clearing condition] read imfb when imfb = 1, then write 0 in imfb 1 [setting conditions] tcnt = grb when grb functions as a compare match register. tcnt value is transferred to grb by an input capture signal, when grb functions as an input capture register. 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt overflowed from h'ffff to h'0000 note: only 0 can be written, to clear the flag. * 490 tcnt0 h/l?imer counter 0 h/l h'68, h'69 itu0 gra0 h/l?eneral register a0 h/l h'6a, h'6b itu0 grb0 h/l?eneral register b0 h/l h'6c, h'6d itu0 tcr1?imer control register 1 h'6e itu1 bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w up-counter 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w output compare or input capture register 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w output compare or input capture register 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: bit functions are the same as for itu0. 491 tior1?imer i/o control register 1 h'6f itu1 tier1?imer interrupt enable register 1 h'70 itu1 tsr1?imer status register 1 h'71 itu1 tcnt1 h/l?imer counter 1 h/l h'72, h'73 itu1 bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imiea 0 r/w 2 ovie 0 r/w 1 imieb 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imfa 0 r/(w) 2 ovf 0 r/(w) 1 imfb 0 r/(w) notes: *** * bit functions are the same as for itu0. only 0 can be written, to clear the flag. bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w note: bit functions are the same as for itu0. 492 gra1 h/l?eneral register a1 h/l h'74, h'75 itu1 grb1 h/l?eneral register b1 h/l h'76, h'77 itu1 tcr2?imer control register 2 h'78 itu2 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu0. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w notes: bit functions are the same as for itu0. when channel 2 is used in phase counting mode, the counter clock source selection by bits tpsc2 to tpsc0 is ignored. 1. 2. 493 tior2?imer i/o control register 2 h'79 itu2 bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w note: bit functions are the same as for itu0. 494 tier2?imer interrupt enable register 2 h'7a itu2 tsr2?imer status register 2 h'7b itu2 tcnt2 h/l?imer counter 2 h/l h'7c, h'7d itu2 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imiea 0 r/w 2 ovie 0 r/w 1 imieb 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imfa 0 r/(w) 2 ovf 0 r/(w) 1 imfb 0 r/(w) overflow flag 0 [clearing condition] *** read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt overflowed from h'ffff to h'0000 or underflowed from h'0000 to h'ffff bit functions are the same as for itu0. note: only 0 can be written, to clear the flag. * bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w phase counting mode: other modes: 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w up/down counter up-counter 495 gra2 h/l?eneral register a2 h/l h'7e, h'7f itu2 grb2 h/l?eneral register b2 h/l h'80, h'81 itu2 tcr3?imer control register 3 h'82 itu3 tior3?imer i/o control register 3 h'83 itu3 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu0. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 cleg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w note: bit functions are the same as for itu0. 496 tier3?imer interrupt enable register 3 h'84 itu3 tsr3?imer status register 3 h'85 itu3 tcnt3 h/l?imer counter 3 h/l h'86, h'87 itu3 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imiea 0 r/w 2 ovie 0 r/w 1 imieb 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imfa 0 r/(w) 2 ovf 0 r/(w) 1 imfb 0 r/(w) *** overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt overflowed from h'ffff to h'0000 or underflowed from h'0000 to h'ffff bit functions are the same as for itu0 note: only 0 can be written, to clear the flag. * bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w complementary pwm mode: other modes: 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w up/down counter up-counter 497 gra3 h/l?eneral register a3 h/l h'88, h'89 itu3 grb3 h/l?eneral register b3 h/l h'8a, h'8b itu3 bra3 h/l?uffer register a3 h/l h'8c, h'8d itu3 brb3 h/l?uffer register b3 h/l h'8e, h'8f itu3 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w output compare or input capture register (can be buffered) 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w output compare or input capture register (can be buffered) 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w used to buffer gra 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w used to buffer grb 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w 498 toer?imer output enable register h'90 itu (all channels) bit initial value read/write 7 1 6 1 5 exb4 1 r/w 4 exa4 1 r/w 3 eb3 1 r/w 0 ea3 1 r/w 2 eb4 1 r/w 1 ea4 1 r/w master enable tioca3 0 tioca output is disabled regardless of tior3, tmdr, and tfcr settings 1 tioca is enabled for output according to tior3, tmdr, and tfcr settings master enable tiocb3 0 tiocb output is disabled regardless of tior3 and tfcr settings 1 tiocb is enabled for output according to tior3 and tfcr settings master enable tioca4 0 tioca output is disabled regardless of tior4, tmdr, and tfcr settings 1 tioca is enabled for output according to tior4, tmdr, and tfcr settings master enable tiocb4 0 tiocb output is disabled regardless of tior4 and tfcr settings 1 tiocb is enabled for output according to tior4 and tfcr settings master enable tocxa4 0 tocxa output is disabled regardless of tfcr settings 1 tocxa is enabled for output according to tfcr settings master enable tocxb4 0 tocxb output is disabled regardless of tfcr settings 1 tocxb is enabled for output according to tfcr settings 4 4 4 4 3 3 4 4 4 4 3 3 499 tocr?imer output control register h'91 itu (all channels) bit initial value read/write 7 1 6 1 5 1 4 1 r/w 3 1 0 ols3 1 r/w 2 1 1 ols4 1 r/w output level select 3 0 tiocb , tocxa , and tocxb outputs are inverted 1 tiocb , tocxa , and tocxb outputs are not inverted output level select 4 0 tioca , tioca , and tiocb outputs are inverted 1 tioca , tioca , and tiocb outputs are not inverted external trigger disable 0 input capture a in channel 1 is used as an external trigger signal in reset-synchronized pwm mode and complementary pwm mode 1 external triggering is disabled xtgd note: * when an external trigger occurs, bits 5 to 0 in toer are cleared to 0, disabling itu output. 3 3 3 3 4 4 4 4 4 4 4 4 * 500 tcr4?imer control register 4 h'92 itu4 tior4?imer i/o control register 4 h'93 itu4 tier4?imer interrupt enable register 4 h'94 itu4 tsr4?imer status register 4 h'95 itu4 bit initial value read/write 7 1 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imiea 0 r/w 2 ovie 0 r/w 1 imieb 0 r/w note: bit functions are the same as for itu0. bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 imfa 0 r/(w) 2 ovf 0 r/(w) 1 imfb 0 r/(w) *** notes: * bit functions are the same as for itu0. only 0 can be written, to clear the flag. 501 tcnt4 h/l?imer counter 4 h/l h'96, h'97 itu4 gra4 h/l?eneral register a4 h/l h'98, h'99 itu4 grb4 h/l?eneral register b4 h/l h'9a, h'9b itu4 bra4 h/l?uffer register a4 h/l h'9c, h'9d itu4 bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w note: bit functions are the same as for itu3. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu3. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu3. bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu3. 502 brb4 h/l?uffer register b4 h/l h'9e, h'9f itu4 tpmr?pc output mode register h'a0 tpc bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w note: bit functions are the same as for itu3. bit initial value read/write 7 1 6 1 5 1 4 1 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 non-overlap 0 normal tpc output in group 3. output values change at compare match a in the selected itu channel. 1 non-overlapping tpc output in group 3, controlled by compare match a and b in the selected itu channel group 2 non-overlap 0 normal tpc output in group 2. output values change at compare match a in the selected itu channel. 1 non-overlapping tpc output in group 2, controlled by compare match a and b in the selected itu channel group 1 non-overlap 0 normal tpc output in group 1. output values change at compare match a in the selected itu channel. 1 non-overlapping tpc output in group 1, controlled by compare match a and b in the selected itu channel group 0 non-overlap 0 normal tpc output in group 0. output values change at compare match a in the selected itu channel. 1 non-overlapping tpc output in group 0, controlled by compare match a and b in the selected itu channel 503 tpcr?pc output control register h'a1 tpc bit initial value read/write 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 0 g0cms0 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w group 3 compare match select 1 and 0 tpc output group 3 (tp to tp ) is triggered by compare match in itu channel 0 tpc output group 3 (tp to tp ) is triggered by compare match in itu channel 2 tpc output group 3 (tp to tp ) is triggered by compare match in itu channel 3 bit 7 0 1 bit 6 0 0 1 itu channel selected as output trigger g3cms1 g3cms0 tpc output group 3 (tp to tp ) is triggered by compare match in itu channel 1 1 15 15 15 15 12 12 12 12 group 2 compare match select 1 and 0 tpc output group 2 (tp to tp ) is triggered by compare match in itu channel 0 tpc output group 2 (tp to tp ) is triggered by compare match in itu channel 2 tpc output group 2 (tp to tp ) is triggered by compare match in itu channel 3 bit 5 0 1 bit 4 0 0 1 itu channel selected as output trigger g2cms1 g2cms0 tpc output group 2 (tp to tp ) is triggered by compare match in itu channel 1 1 11 11 11 11 8 8 8 8 group 1 compare match select 1 and 0 tpc output group 1 (tp to tp ) is triggered by compare match in itu channel 0 tpc output group 1 (tp to tp ) is triggered by compare match in itu channel 2 tpc output group 1 (tp to tp ) is triggered by compare match in itu channel 3 bit 3 0 1 bit 2 0 0 1 itu channel selected as output trigger g1cms1 g1cms0 tpc output group 1 (tp to tp ) is triggered by compare match in itu channel 1 1 7 7 7 7 4 4 4 4 group 0 compare match select 1 and 0 tpc output group 0 (tp to tp ) is triggered by compare match in itu channel 0 tpc output group 0 (tp to tp ) is triggered by compare match in itu channel 2 tpc output group 0 (tp to tp ) is triggered by compare match in itu channel 3 bit 1 0 1 bit 0 0 0 1 itu channel selected as output trigger g0cms1 g0cms0 tpc output group 0 (tp to tp ) is triggered by compare match in itu channel 1 1 3 3 3 3 0 0 0 0 504 nderb?ext data enable register b h'a2 tpc ndera?ext data enable register a h'a3 tpc bit initial value read/write 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 0 nder8 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w next data enable 15 to 8 tpc outputs tp to tp are disabled (ndr15 to ndr8 are not transferred to pb to pb ) tpc outputs tp to tp are enabled (ndr15 to ndr8 are transferred to pb to pb ) bits 7 to 0 0 1 description nder15 to nder8 15 15 8 8 7 7 0 0 bit initial value read/write 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 0 nder0 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w next data enable 7 to 0 tpc outputs tp to tp are disabled (ndr7 to ndr0 are not transferred to pa to pa ) tpc outputs tp to tp are enabled (ndr7 to ndr0 are transferred to pa to pa ) bits 7 to 0 0 1 description nder7 to nder0 7 7 0 0 7 7 0 0 505 ndrb?ext data register b h'a4/h'a6 tpc same output trigger for tpc output groups 2 and 3 address h'ffa4 address h'ffa6 different output triggers for tpc output groups 2 and 3 address h'ffa4 address h'ffa6 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w next output data for tpc output group 3 next output data for tpc output group 2 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 1 0 1 2 1 1 1 next output data for tpc output group 3 bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w next output data for tpc output group 2 506 ndra?ext data register a h'a5/h'a7 tpc same output trigger for tpc output groups 0 and 1 address h'ffa5 address h'ffa7 different output triggers for tpc output groups 0 and 1 address h'ffa5 address h'ffa7 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w next output data for tpc output group 1 next output data for tpc output group 0 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 1 0 1 2 1 1 1 next output data for tpc output group 1 bit initial value read/write 7 1 6 1 5 1 4 1 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w next output data for tpc output group 0 507 tcsr?imer control/status register h'a8 wdt bit initial value read/write 7 ovf 0 r/(w) 6 wt/ 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w overflow flag timer mode select it 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt changes from h'ff to h'00 0 interval timer: requests interval timer interrupts 1 watchdog timer: generates a reset signal clock select 2 to 0 0 1 ?2 ?32 ?64 ?128 ?256 ?512 ?2048 0 1 0 1 0 1 0 1 0 1 0 ?4096 1 timer enable 0 timer disabled 1 timer enabled tcnt is initialized to h'00 and halted tcnt is counting cpu interrupt requests are enabled note: only 0 can be written, to clear the flag. * * 508 tcnt?imer counter h'a9 (read), wdt h'a8 (write) rstcsr?eset control/status register h'ab (read), wdt h'aa (write) bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value bit initial value read/write 7 wrst 0 r/(w) 6 rstoe 0 r/w 5 1 4 1 3 1 0 1 2 1 1 1 reset output enable 0 reset signal is not output externally 1 reset signal is output externally watchdog timer reset 0 [clearing condition] reset signal input at pin, or 0 written by software 1 [setting condition] tcnt overflow generates a reset signal note: only 0 can be written in bit 7, to clear the flag. * * res 509 smr?erial mode register h'b0 sci bit initial value read/write 7 c/ 0 r/w 6 chr 0 r/w 5 pe 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w parity enable clock select 1 and 0 cks1 clock source cks0 bit 0 bit 1 0 1 ?clock ?4 clock ?16 clock ?64 clock 0 0 1 1 a 7 o/ 0 r/w e 0 parity bit is not added or checked 1 parity bit is added and checked parity mode 0 even parity 1 odd parity stop bit length multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected 0 one stop bit 1 two stop bits character length 0 8-bit data 1 7-bit data communication mode 0 asynchronous mode 1 synchronous mode 510 brr?it rate register h'b1 sci bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w serial communication bit rate setting 511 scr?erial control register h'b2 sci bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w transmit interrupt enable 0 transmit-data-empty interrupt request (txi) is disabled 1 transmit-data-empty interrupt request (txi) is enabled receive interrupt enable 0 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled transmit enable clock enable 1 and 0 cke1 multiprocessor interrupt enable 0 1 clock selection and output asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode bit 1 cke2 0 1 0 1 bit 2 receive enable synchronous mode 0 multiprocessor interrupts are disabled (normal receive operation) 1 multiprocessor interrupts are enabled 0 transmitting is disabled 1 transmitting is enabled transmit-end interrupt enable 0 transmitting is disabled 1 transmitting is enabled 0 transmit-end interrupt requests (tei) are disabled 1 transmit-end interrupt requests (tei) are enabled internal clock, sck pin available for generic input internal clock, sck pin used for serial clock outpu t internal clock, sck pin used for clock output internal clock, sck pin used for serial clock outpu t external clock, sck pin used for clock input external clock, sck pin used for serial clock input external clock, sck pin used for clock input external clock, sck pin used for serial clock input 512 tdr?ransmit data register h'b3 sci bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w serial transmit data 513 ssr?erial status register h'b4 sci bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r transmit end 0 [clearing conditions] 1 [setting conditions] reset or transition to standby mode. te is cleared to 0 in scr. tdre is 1 when last bit of serial character is transmitted. * * * * * multiprocessor bit transfer read tdre when tdre = 1, then write 0 in tdre. multiprocessor bit parity error 0 [clearing conditions] 1 [setting condition] parity error: (parity of receive data does not match parity setting of o/ in smr) reset or transition to standby mode. read per when per = 1, then write 0 in per. e framing error 0 [clearing conditions] 1 [setting condition] framing error (stop bit is 0) reset or transition to standby mode. read fer when fer = 1, then write 0 in fer. overrun error 0 [clearing conditions] 1 [setting condition] overrun error (reception of next serial data ends when rdrf = 1) reset or transition to standby mode. read orer when orer = 1, then write 0 in orer. receive data register full 0 [clearing conditions] 1 [setting condition] serial data is received normally and transferred from rsr to rdr reset or transition to standby mode. read rdrf when rdrf = 1, then write 0 in rdrf. transmit data register empty 0 [clearing conditions] 1 [setting conditions] reset or transition to standby mode. te is 0 in scr data is transferred from tdr to tsr, enabling new data to be written in tdr. read tdre when tdre = 1, then write 0 in tdre. 0 multiprocessor bit value in receive data is 0 1 multiprocessor bit value in receive data is 1 0 multiprocessor bit value in transmit data is 0 1 multiprocessor bit value in transmit data is 1 note: only 0 can be written, to clear the flag. * 514 rdr?eceive data register h'b5 sci p1ddr?ort 1 data direction register h'c0 port 1 p2ddr?ort 2 data direction register h'c1 port 2 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r serial receive data bit initial value read/write 7 p1 7 ddr 0 w 6 p1 6 ddr 0 w 5 p1 5 ddr 0 w 4 p1 4 ddr 0 w 3 p1 3 ddr 0 w 0 p1 0 ddr 0 w 2 p1 2 ddr 0 w 1 p1 1 ddr 0 w port 1 input/output select 0 generic input 1 generic output bit initial value read/write 7 p2 7 ddr 0 w 6 p2 6 ddr 0 w 5 p2 5 ddr 0 w 4 p2 4 ddr 0 w 3 p2 3 ddr 0 w 0 p2 0 ddr 0 w 2 p2 2 ddr 0 w 1 p2 1 ddr 0 w port 2 input/output select 0 generic input 1 generic output 515 p1dr?ort 1 data register h'c2 port 1 p2dr?ort 2 data register h'c3 port 2 p3ddr?ort 3 data direction register h'c4 port 3 516 bit initial value read/write 7 p1 7 0 r/w 6 p1 6 0 r/w 5 p1 5 0 r/w 4 p1 4 0 r/w 3 p1 3 0 r/w 0 p1 0 0 r/w 2 p1 2 0 r/w 1 p1 1 0 r/w data for port 1 pins bit initial value read/write 7 p2 7 0 r/w 6 p2 6 0 r/w 5 p2 5 0 r/w 4 p2 4 0 r/w 3 p2 3 0 r/w 0 p2 0 0 r/w 2 p2 2 0 r/w 1 p2 1 0 r/w data for port 2 pins bit initial value read/write 7 p3 7 ddr 0 w 6 p3 6 ddr 0 w 5 p3 5 ddr 0 w 4 p3 4 ddr 0 w 3 p3 3 ddr 0 w 0 p3 0 ddr 0 w 2 p3 2 ddr 0 w 1 p3 1 ddr 0 w port 3 input/output select 0 generic input 1 generic output p3dr?ort 3 data register h'c6 port 3 p5ddr?ort 5 data direction register h'c8 port 5 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 p5 ddr 0 w 3 2 p5 ddr 0 w 2 1 p5 ddr 0 w 1 0 p5 ddr 0 w 0 port 5 input/output select 0 generic input 1 generic output 517 bit initial value read/write 7 p3 7 0 r/w 6 p3 6 0 r/w 5 p3 5 0 r/w 4 p3 4 0 r/w 3 p3 3 0 r/w 0 p3 0 0 r/w 2 p3 2 0 r/w 1 p3 1 0 r/w data for port 3 pins p6ddr?ort 6 data direction register h'c9 port 6 p5dr?ort 5 data register h'ca port 5 p6dr?ort 6 data register h'cb port 6 bit initial value read/write 7 ? 1 6 ? 0 w 5 p6 5 ddr 0 w 4 p6 4 ddr 0 w 3 p6 3 ddr 0 w 0 p6 0 ddr 0 w 2 ? 0 w 1 ? 0 w port 6 input/output select 0 generic input 1 generic output bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 p5 0 r/w 3 2 p5 0 r/w 2 1 p5 0 r/w 1 0 p5 0 r/w 0 data for port 5 pins bit initial value read/write 7 ? 1 6 ? 0 r/w 5 p6 0 r/w 5 4 p6 0 r/w 4 3 p6 0 r/w 3 2 ? 0 r/w 1 ? 0 r/w 0 p6 0 r/w 0 data for port 6 pins 518 p8ddr?ort 8 data direction register h'cd port 8 p7dr?ort 7 data register h'ce port 7 p8dr?ort 8 data register h'cf port 8 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 p8 ddr 0 w 4 3 p8 ddr 0 w 3 2 p8 ddr 0 w 2 1 p8 ddr 0 w 1 0 p8 ddr 0 w 0 port 8 input/output select 0 generic input 1 generic output bit initial value read/write 0 p7 ? r * note: determined by pins p7 to p7 . * 0 1 p7 ? r * 1 2 p7 ? r * 2 3 p7 ? r * 3 4 p7 ? r * 4 5 p7 ? r * 5 6 p7 ? r * 6 7 p7 ? r * 7 data for port 7 pins 70 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 0 r/w 3 p8 0 r/w 3 2 p8 0 r/w 2 1 p8 0 r/w 1 0 p8 0 r/w 0 data for port 8 pins 519 p9ddr?ort 9 data direction register h'd0 port 9 paddr?ort a data direction register h'd1 port a p9dr?ort 9 data register h'd2 port 9 bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 w 4 p9 ddr 0 w 4 3 ? 0 w 2 p9 ddr 0 w 2 1 ? 0 w 0 p9 ddr 0 w 0 port 9 input/output select 0 generic input 1 generic output bit initial value read/write 7 pa ddr 0 w 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 port a input/output select 0 generic input 1 generic output bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 r/w 4 p9 0 r/w 4 3 ? 0 r/w 2 p9 0 r/w 2 1 ? 0 r/w 0 p9 0 r/w 0 data for port 9 pins 520 padr?ort a data register h'd3 port a pbddr?ort b data direction register h'd4 port b pbdr?ort b data register h'd6 port b bit initial value read/write 0 pa 0 r/w 0 1 pa 0 r/w 1 2 pa 0 r/w 2 3 pa 0 r/w 3 4 pa 0 r/w 4 5 pa 0 r/w 5 6 pa 0 r/w 6 7 pa 0 r/w 7 data for port a pins bit initial value read/write 7 pb ddr 0 w 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 port b input/output select 0 generic input 1 generic output 521 bit initial value read/write 0 pb 0 r/w 0 1 pb 0 r/w 1 2 pb 0 r/w 2 3 pb 0 r/w 3 4 pb 0 r/w 4 5 pb 0 r/w 5 6 pb 0 r/w 6 7 pb 0 r/w 7 data for port b pins p2pcr?ort 2 input pull-up control register h'd8 port 2 p5pcr?ort 5 input pull-up control register h'db port 5 addra h/l?/d data register a h/l h'e0, h'e1 a/d bit initial value read/write 7 p2 pcr 0 r/w 7 6 p2 pcr 0 r/w 6 5 p2 pcr 0 r/w 5 4 p2 pcr 0 r/w 4 3 p2 pcr 0 r/w 3 2 p2 pcr 0 r/w 2 1 p2 pcr 0 r/w 1 0 p2 pcr 0 r/w 0 port 2 input pull-up control 7 to 0 0 input pull-up transistor is off 1 input pull-up transistor is on note: valid when the corresponding p2ddr bit is cleared to 0 (designating generic input). 522 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 p5 pcr 0 r/w 3 2 p5 pcr 0 r/w 2 1 p5 pcr 0 r/w 1 0 p5 pcr 0 r/w 0 port 5 input pull-up control 3 to 0 0 input pull-up transistor is off 1 input pull-up transistor is on note: valid when the corresponding p5ddr bit is cleared to 0 (designating generic input). bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r a/d conversion data 10-bit data giving an a/d conversion result addrah addral addrb h/l?/d data register b h/l h'e2, h'e3 a/d addrc h/l?/d data register c h/l h'e4, h'e5 a/d addrd h/l?/d data register d h/l h'e6, h'e7 a/d bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r addrbh addrbl a/d conversion data 10-bit data giving an a/d conversion result bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r addrch addrcl a/d conversion data 10-bit data giving an a/d conversion result bit initial value read/write 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r addrdh addrdl a/d conversion data 10-bit data giving an a/d conversion result 523 adcr?/d control register h'e9 a/d bit initial value read/write 7 trge 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 trigger enable 0 a/d conversion cannot be externally triggered 1 a/d conversion starts at the fall of the external trigger signal ( ) adtrg 524 adcsr?/d control/status register h'e8 a/d bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * note: only 0 can be written, to clear flag. * channel select 2 to 0 ch2 1 single mode an an an an an an an ch1 0 1 0 1 channel selection ch0 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 an 7 scan mode an an , an an to an an to an an an , an an to an 0 0 0 0 4 4 4 an to an 4 1 5 2 3 6 7 description group selection a/d end flag a/d interrupt enable a/d start clock select scan mode 0 [clearing condition] read adf while adf = 1, then write 0 in adf 1 [setting conditions] single mode: scan mode: 0 a/d end interrupt request is disabled 1 a/d end interrupt request is enabled 0 a/d conversion is stopped 1 single mode: scan mode: 0 single mode 1 scan mode 0 conversion time = 266 states (maximum) 1 conversion time = 134 states (maximum) a/d conversion ends a/d conversion ends in all selected channels a/d conversion starts; adst is automatically cleared to 0 when conversion ends a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode 525 astcr?ccess state control register h'ed bus controller wcr?ait control register h'ee bus controller bit initial value read/write 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w area 7 to 0 access state control areas 7 to 0 are two-state access areas areas 7 to 0 are three-state access areas bits 7 to 0 0 1 number of states in access cycle ast7 to ast0 526 bit initial value read/write 7 1 6 1 5 1 4 1 3 wms1 0 r/w 0 wc0 1 r/w 2 wms0 0 r/w 1 wc1 1 r/w wait count 1 and 0 wc1 number of wait states wc0 bit 0 bit 1 0 1 no wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted 0 0 1 1 wait mode select 1 and 0 wms1 wait mode wms0 bit 2 bit 3 0 1 programmable wait mode no wait states inserted by wait-state controller pin wait mode pin auto-wait mode 0 0 1 1 wcer?ait controller enable register h'ef bus controller mdcr?ode control register h'f1 system control bit initial value read/write 7 wce7 1 r/w 6 wce6 1 r/w 5 wce5 1 r/w 4 wce4 1 r/w 3 wce3 1 r/w 0 wce0 1 r/w 2 wce2 1 r/w 1 wce1 1 r/w wait state controller enable 7 to 0 0 wait-state control is disabled (pin wait mode 0) 1 wait-state control is enabled 527 bit initial value read/write 7 ? 1 6 ? 1 5 ? 0 4 ? 0 3 ? 0 0 mds0 ? r 2 ? 1 1 mds1 ? r * * note: determined by the state of the mode pins (md and md ). * mode select 1 and 0 10 operating mode mode 1 mode 2 mode 3 md 1 0 1 bit 1 md 0 0 1 0 1 bit 0 syscr?ystem control register h'f2 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ? 1 software standby 0 sleep instruction causes transition to sleep mode 1 sleep instruction causes transition to software standby mode standby timer select 2 to 0 sts2 0 1 standby timer waiting time = 8192 states waiting time = 16384 states waiting time = 32768 states waiting time = 65536 states waiting time = 131072 states illegal setting bit 6 sts1 0 1 0 1 bit 5 sts0 0 1 0 1 bit 4 ram enable 0 on-chip ram is disabled 1 on-chip ram is enabled nmi edge select 0 an interrupt is requested at the falling edge of nmi 1 an interrupt is requested at the rising edge of nmi user bit enable 0 ccr bit 6 (ui) is used as an interrupt mask bit 1 ccr bit 6 (ui) is used as a user bit 528 iscr?rq sense control register h'f4 interrupt controller ier?rq enable register h'f5 interrupt controller bit initial value read/write 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc 0 r/w irq to irq sense control 0 interrupts are requested when irq to irq inputs are low 1 interrupts are requested by falling-edge input at irq to irq 40 4 4 0 0 bit initial value read/write 7 ? 0 r/(w) 6 ? 0 r/(w) 5 ? 0 r/(w) 4 irq4e 0 r/(w) 3 irq3e 0 r/(w) 2 irq2e 0 r/(w) 1 irq1e 0 r/(w) 0 irq0e 0 r/(w) irq to irq enable 0 irq to irq interrupts are disabled 1 irq to irq interrupts are enabled 40 4 4 0 0 529 isr?rq status register h'f6 interrupt controller initial value read/write ? 0 ? 0 ? 0 irq4f 0 r/(w) * irq3f 0 r/(w) * irq2f 0 r/(w) * irq1f 0 r/(w) * irq0f 0 r/(w) * irq to irq flags bits 4 to 0 0 1 setting and clearing conditions irq4f to irq0f [clearing conditions] read irqnf when irqnf = 1, then write 0 in irqnf. irqnsc = 0, input is high, and interrupt exception handling is carried out. irqnsc = 1 and irqn interrupt exception handling is carried out. [setting conditions] irqnsc = 0 and input is low. irqnsc = 1 and input changes from high to low. (n = 4 to 0 ) irqn irqn irqn 40 note: only 0 can be written, to clear the flag. * 530 ipra?nterrupt priority register a h'f8 interrupt controller interrupt sources controlled by each bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 interrupt irq 0 irq 1 irq 2 , irq 4 wdt itu itu itu source irq 3 chan- chan- chan- nel 0 nel 1 nel 2 iprb?nterrupt priority register b h'f9 interrupt controller interrupt sources controlled by each bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iprb7 iprb6 iprb3 iprb1 interrupt itu itu ? ? sci a/d source chan- chan- chan- con- nel 3 nel 4 nel verter bit initial value read/write 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 0 ipra0 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w priority level a7 to a0 0 priority level 0 (low priority) 1 priority level 1 (high priority) bit initial value read/write 7 iprb7 0 r/w 6 iprb6 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 iprb3 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 iprb1 0 r/w priority level b7, b6, b3, and b1 0 priority level 0 (low priority) 1 priority level 1 (high priority) 531 appendix c i/o port block diagrams c.1 port 1 block diagram figure c-1 port 1 block diagram 532 internal data bus (upper) internal data bus (lower) p1 n ddr reset mode 1/2/3 r qd c reset r qd p1 n ddr wp1d wp1 c rp1 mode 1 mode 2/3 mode 2/3 p1 n * software standby hardware standby wp1d: wp1: rp1: n = 0 to 7 * : write to p1ddr write to port 1 read port 1 set priority c.2 port 2 block diagram figure c-2 port 2 block diagram 533 internal data bus (upper) internal data bus (lower) p2 n ddr reset mode 1/2/3 r qd c reset r qd p2 n dr wp2d wp2 c rp2 mode 1 mode 2/3 mode 2/3 p2 n * software standby hardware standby wp2p: rp2p: wp2d: wp2: rp2: n = 0 to 7 * : write to p2pcr read p2pcr write to p2ddr write to port 2 read port 2 set priority reset r qd p2 n pcr wp2p c rp2p c.3 port 3 block diagram figure c-3 port 3 block diagram 534 internal data bus (upper) internal data bus (lower) p3 n ddr reset mode 2/3 r qd c reset r qd p3 n dr wp3d wp3 c rp3 mode 1 mode 2/3 p3 n wp3d: wp3: rp3: n = 0 to 7 write to p3ddr write to port 3 read port 3 write to external address hardware standby read external address c.4 port 5 block diagram figure c-4 port 5 block diagram 535 internal data bus (upper) internal data bus (lower) p5 n ddr reset mode 1 to mode 3 r qd c reset r qd p5 n dr wp5d wp5 c rp5 mode 1 mode 2/3 mode 2/3 p5 n * software standby hardware standby wp5p: rp5p: wp5d: wp5: rp5: n = 0 to 3 * : write to p5pcr read p5pc4 write to p5ddr write to port 5 read port 5 set priority reset r qd p5 n pcr wp5p c rp5p c.5 port 6 block diagram figure c-5 (a) port 6 block diagram (pin p6 0 ) 536 p6 0 ddr reset r qd c reset r qd p6 0 dr wp6d wp6 c rp6 p6 0 wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 internal data bus bus controller wait input enable bus controller wait input mode 2/3 figure c-5 (b) port 6 block diagram (pins p6 1 to p6 3 ) 537 internal data bus p6 n ddr reset r qd c reset r qd p6 n dr wp6d wp6 c rp6 mode 2/3 mode 2/3 p6 n software standby hardware standby wp6d: wp6: rp6: n = 5 to 3 write to p6ddr write to port 6 read port 6 as output rd output wr output mode 1 c.6 port 7 block diagram figure c-6 (a) port 7 block diagram 538 internal data bus p7 n rp7: read port 7 n = 0 to 7 a/d converter analog input rp7 input enable c.7 port 8 block diagram figure c-7 port 8 block diagram (pin p8 0 ) 539 internal data bus p8 0 ddr reset r qd c reset r qd p8 0 dr wp8d wp8 c rp8 p8 0 wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 interrupt controller irq 0 input c.8 port 9 block diagram figure c-8 (a) port 9 block diagram (pin p9 0 ) 540 internal data bus p9 0 ddr reset qd c reset r qd p9 0 dr wp9d wp9 c rp9 p9 0 wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 sci r output enable serial data figure c-8 (b) port 9 block diagram (pins p9 2 , p9 3 ) 541 internal data bus p9 2 ddr reset qd c reset r qd p9 2 dr wp9d wp9 c rp9 p9 2 wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 sci r input enable serial data figure c-8 (c) port 9 block diagram (pin p9 4 ) 542 internal data bus p9 4 ddr reset qd c reset r qd p9 4 dr wp9d wp9 c rp9 p9 4 wp9d: wp9: rp9: n = 4, 5 write to p9ddr write to port 9 read port 9 sci r clock input enable clock output clock output enable clock input interrupt controller irq 4 input c.9 port a block diagram figure c-9 (a) port a block diagram (pins pa 0 , pa 1 ) 543 internal data bus pa n ddr reset qd c reset r qd pa n dr wpad c pa n wpad: wpa: rpa: n = 0, 1 write to paddr write to port a read port a tpc r tpc output enable output trigger next data counter input clock rpa wpa itu figure c-9 (b) port a block diagram (pins pa 2 , pa 3 ) 544 internal data bus pa n ddr reset qd c reset r qd pa n dr wpad c pa n wpad: wpa: rpa: n = 2, 3 write to paddr write to port a read port a tpc r tpc output enable output trigger next data input capture input rpa wpa itc output enable compare match output counter input clock figure c-9 (c) port a block diagram (pins pa 4 , pa 7 ) 545 pa n ddr reset q d c reset r qd pa n dr wpad c pa n wpad: wpa: rpa: n = 4 to 7 write to paddr write to port a read port a r rpa wpa internal data bus tpc tpc output enable output trigger next data itu output enable compare match input input capture input c.10 port b block diagram figure c-10 (a) port b block diagram (pins pb 0 to pb 3 ) 546 internal data bus pb n ddr reset qd c reset r qd pb n dr wpbd c pb n wpbd: wpb: rpb: n = 0 to 3 write to pbddr write to port b read port b tpc r tpc output enable output trigger next data rpb wpb itc compare match output input capture input output enable figure c-10 (b) port b block diagram (pins pb 4 , pb 5 ) 547 internal data bus pb n ddr reset qd c reset r qd pb n dr wpbd c pb n wpbd: wpb: rpb: n = 4 to 5 write to pbddr write to port b read port b tpc r tpc output enable output trigger next data rpb wpb itu output enable compare match output figure c-10 (c) port b block diagram (pin pb 6 ) 548 pb 6 ddr reset q d c reset r qd pb 6 dr wpbd c pb 6 wpbd: wpb: rpb: write to pbddr write to port b read port b tpc r tpc output enable output trigger next data rpb wpb internal data bus figure c-10 (d) port b block diagram (pin pb 7 ) 549 pb 7 ddr reset q d c reset r qd pb 7 dr wpbd c pb 7 wpbd: wpb: rpb: write to pbddr write to port b read port b tpc r tpc output enable output trigger next data rpb wpb internal data bus a/d converter adtrg input appendix d pin states d.1 port states in each mode table d-1 port states hardware software program pin reset standby standby sleep execution name mode state mode mode mode sleep mode clock output t h clock output clock output p1 7 to p1 0 1 t t keep keep input port (ddr = 0) t keep a 7 to a 0 (ddr = 1) 2, 3 t t keep keep i/o port p2 7 to p2 0 1 t t keep keep input port (ddr = 0) t keep a 15 to a 8 (ddr = 1) 2, 3 t t keep keep i/o port p3 7 to p3 0 1ttttd 7 to d 0 2, 3 t t keep keep i/o port p5 3 to p5 0 1 t t keep keep input port (ddr = 0) t keep a 19 to a 16 (ddr = 1) 2, 3 t t keep keep i/o port p6 0 1 wait pin t t wait generic t t t t i/o port i/o pin 2, 3 t t t t i/o port p6 5 to p6 3 1htth wr , rd , as 2, 3 t t keep keep i/o port legend h: high l: low t: high-impedance state keep: input pins are in the high-impedance state; output pins maintain their previous state. ddr: data direction register bit 550 table d-1 port states (cont) hardware software program pin reset standby standby sleep execution name mode state mode mode mode sleep mode p7 7 to p7 0 1 to 3 t t t t input port p8 3 to p8 0 1 to 3 t t keep keep i/o port p9 4 , p9 2 , 1 to 3 t t keep keep i/o port p9 0 pa 7 to pa 0 1 to 3 t t keep keep i/o port pb 7 to pb 0 1 to 3 t t keep keep i/o port legend h: high l: low t: high-impedance state keep: input pins are in the high-impedance state; output pins maintain their previous state. ddr: data direction register bit 551 d.2 pin states at reset reset in t 1 state: figure d-1 is a timing diagram for the case in which res goes low during the t 1 state of an external memory access cycle. as soon as res goes low, all ports are initialized to the input state. as , rd , and wr go high, and the data bus goes to the high-impedance state. the address bus is initialized to the low output level 0.5 state after the low level of res is sampled. sampling of res takes place at the fall of the system clock (?. figure d-1 reset during memory access (reset during t 1 state) access to external address ? res h'000000 high impedance high impedance high high high internal reset signal t 1 t 2 t 3 rd (read access) (mode 1) wr (write access) (mode 1) data bus (write access) (mode 1) i/o port (modes 1 to 3) address bus (mode 1) as (mode 1) 552 reset in t 2 state: figure d-2 is a timing diagram for the case in which res goes low during the t 2 state of an external memory access cycle. as soon as res goes low, all ports are initialized to the input state. as , rd , and wr go high, and the data bus goes to the high-impedance state. the address bus is initialized to the low output level 0.5 state after the low level of res is sampled. the same timing applies when a reset occurs during a wait state (t w ). figure d-2 reset during memory access (reset during t 2 state) ? res h'000000 high impedance high impedance internal reset signal access to external address t 1 t 2 t 3 rd (read access) (mode 1) wr (write access) (mode 1) data bus (write access) (mode 1) i/o port (modes 1 to 3) address bus (mode 1) as (mode 1) 553 reset in t 3 state: figure d-3 is a timing diagram for the case in which res goes low during the t 3 state of an external memory access cycle. as soon as res goes low, all ports are initialized to the input state. as , rd , and wr go high, and the data bus goes to the high-impedance state. the address bus outputs are held during the t 3 state.the same timing applies when a reset occurs in the t 2 state of an access cycle to a two-state-access area. figure d-3 reset during memory access (reset during t 3 state) ? res high impedance high impedance internal reset signal access to external address t 1 t 2 t 3 h'000000 rd (read access) (mode 1) wr (write access) (mode 1) data bus (write access) (mode 1) i/o port (modes 1 to 3) address bus (mode 1) as (mode 1) 554 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). (2) to retain ram contents with the rame bit cleared to 0 in syscr, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. t 1 3 10t cyc t 2 3 0 ns stby res stby res t = 100 ns t osc 555 appendix f package dimensions figure f-1 shows the fp-80a package dimensions of the h8/3032 series, and figure f-2 shows the tfp-80c package dimensions. unit: mm figure f-1 package dimensions (fp-80a) unit: mm figure f-2 package dimensions (tfp-80c) 60 0 ?5 0.10 0.12 m 17.2 ?0.3 41 61 80 1 20 40 21 17.2 0.3 0.30 0.10 0.65 3.05 max 0.10 1.60 0.80 ?0.30 14.0 2.70 +0.20 ?.16 0.17 +0.08 ?.05 0.10 m 0.10 0.50 ?0.10 0 ?5 1.20 max 0.00 min 0.20 max 14.0 ?0.2 0.50 12.0 14.0 ?0.2 60 41 120 80 61 21 40 0.17 ?0.05 1.00 0.20 ?0.05 556 |
Price & Availability of HD6473032F
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |